参数资料
型号: ADS62P45IRGCT
厂商: Texas Instruments
文件页数: 16/78页
文件大小: 0K
描述: IC ADC 14BIT DUAL 125MSPS 64VQFN
产品培训模块: Data Converter Basics
标准包装: 1
位数: 14
采样率(每秒): 125M
数据接口: 串行,并联
转换器数目: 2
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-VFQFN 裸露焊盘
供应商设备封装: 64-VQFN 裸露焊盘(9x9)
包装: 标准包装
输入数目和类型: 2 个差分,单极
其它名称: 296-23138-6
SLAS561C
– JULY 2007 – REVISED FEBRUARY 2012
Table 13.
A7
–A0
D7
D6
D5
D4
D3
D2
D1
D0
(hex)
<OUTPUT
<REF>
<OVRD>
INTERFACE
>
<COARSE GAIN>
<POWER DOWN
14
0
Internal / External
MODES
>
Over-ride bit
LVDS or CMOS
3.5 dB gain
reference
interface
D2-D0
<POWER DOWN MODES>
000
Normal operation
001
Channel A output buffer disabled
010
Channel B output buffer disabled
011
Channel A and B output buffers disabled
100
Global power down
101
Channel A standby
110
Channel B standby
111
Multiplexed mode, MUX
– (only with CMOS interface)
Channel A and B data is multiplexed and output on DB13 to DB0 pins.
D3
<REF> Reference mode
0
Internal reference enabled
1
External reference enabled
D4
<COARSE GAIN> Coarse gain control
0
0 dB coarse gain
1
3.5 dB coarse gain
D5
<OUTPUT INTERFACE> Output interface selection
0
Parallel CMOS data outputs
1
DDR LVDS data outputs
D7
<OVRD> Over-ride bit – the LVDS/CMOS selection, power down and MUX modes can also be controlled using parallel pins.
By setting
<OVRD> = 1, register bits LVDS <CMOS> and <POWER DOWN MODES> will over-ride the settings of the
parallel pins.
0
Disable over-ride
1
Enable over-ride
Table 14.
A7
–A0
D7
D6
D5
D4
D3
D2
D1
D0
(hex)
DATA FORMAT
>
16
0
Bit / Byte wise (LVDS only)
<TEST PATTERNS>
2s complement or straight binary
Copyright
2007–2012, Texas Instruments Incorporated
23
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