参数资料
型号: ADS62P45IRGCT
厂商: Texas Instruments
文件页数: 48/78页
文件大小: 0K
描述: IC ADC 14BIT DUAL 125MSPS 64VQFN
产品培训模块: Data Converter Basics
标准包装: 1
位数: 14
采样率(每秒): 125M
数据接口: 串行,并联
转换器数目: 2
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-VFQFN 裸露焊盘
供应商设备封装: 64-VQFN 裸露焊盘(9x9)
包装: 标准包装
输入数目和类型: 2 个差分,单极
其它名称: 296-23138-6
SLAS561C
– JULY 2007 – REVISED FEBRUARY 2012
COARSE GAIN AND PROGRAMMABLE FINE GAIN
ADS62P4X includes gain settings that can be used to get improved SFDR performance (over 0dB gain mode).
For each gain setting, the analog input full-scale range scales proportionally, as shown in Table 20.
The coarse gain is a fixed setting of 3.5 dB and is designed to improve SFDR with little degradation in SNR. The
fine gain is programmable in 0.5 dB steps from 0 to 6 dB; however the SFDR improvement is achieved at the
expense of SNR. So, the programmable fine gain makes it possible to trade-off between SFDR and SNR. The
coarse gain makes it possible to get best SFDR but without losing SNR significantly.
The gains can be programmed using the serial interface (bits COARSE GAIN and FINE GAIN). Note that the
default gain after reset is 0 dB.
Table 20. Full-Scale Range Across Gains
GAIN, dB
TYPE
FULL-SCALE, VPP
0
Default after reset
2V
3.5
Coarse (fixed)
1.34
0.5
1.89
1.0
1.78
1.5
1.68
2.0
1.59
2.5
1.50
3.0
1.42
Fine (programmable)
3.5
1.34
4.0
1.26
4.5
1.19
5.0
1.12
5.5
1.06
6.0
1.00
CLOCK INPUT
The clock inputs can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS), with little or
no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM using
internal 5-k
resistors as shown in Figure 90. This allows using transformer-coupled drive circuits for sine wave
clock or ac-coupling for LVPECL, LVDS clock sources (Figure 92 and Figure 93).
52
Copyright
2007–2012, Texas Instruments Incorporated
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