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| 型号： | ADS7883SDBVT |
| 厂商： | Texas Instruments |
| 文件页数： | 14/19页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 3MSPS SOT23-6 |
| 产品培训模块： | Data Converter Basics |
| 标准包装： | 1 |
| 位数： | 12 |
| 采样率（每秒）： | 3M |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 20mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-6 |
| 供应商设备封装： | SOT-23-6 |
| 包装： | 标准包装 |
| 输入数目和类型： | 1 个单端，单极 |
| 产品目录页面： | 892 (CN2011-ZH PDF) |
| 其它名称： | 296-23635-6 |
TIMING REQUIREMENTS (see Figure 21)
SLAS594 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com
ELECTRICAL SPECIFICATIONS (continued)
VDD = 2.7 V to 5.5 V, TA = –40°C to 125°C, fsample = 2 MSPS for VDD = 2.7 V to 4.5 V, fsample = 3 MSPS for VDD = 4.5 V to 5.5
V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
At VDD = 3 V, 2-MSPS throughput
2.15
3
At VDD = 3 V, Static state
1.8
Supply current (normal mode)
mA
At VDD = 5 V, 3-MSPS throughput
2.7
4
At VDD = 5 V, Static state
2
SCLK off
1
Power-down state supply current
A
SCLK on (48 MHz)
90
250
VDD = 5 V, 3 MSPS
13.5
20
Power dissipation
mW
VDD = 3 V, 2 MSPS
6.45
VDD = 5 V
10
12.5
Power dissipation in static state
mW
VDD = 3 V
5.4
Power-down time
0.1
s
Power-up time
0.8
s
TEMPERATURE RANGE
Specified performance
–40
125
°C
All specifications typical at TA = –40°C to 125°C, VDD = 2.7 V to 5.5 V, unless otherwise specified.
PARAMETER
TEST CONDITIONS(1)
MIN
TYP
MAX
UNIT
VDD = 3 V
13.5 × tSCLK
tconv
Conversion time
ns
VDD = 5 V
13.5 × tSCLK
VDD = 3 V
78
tacq
Aquisition time
ns
VDD = 5 V
52
VDD = 3 V
10
Minimum quiet time needed from bus 3-state to start
tq
ns
of next conversion
VDD = 5 V
10
VDD = 3 V
9
15
td1
Delay time, CS low to first data (0) out
ns
VDD = 5 V
8
11
VDD = 3 V
7
tsu1
Setup time, CS low to SCLK low
ns
VDD = 5 V
5
VDD = 3 V
11
20
td2
Delay time, SCLK falling to SDO
ns
VDD = 5 V
9
12
VDD < 3 V
5.5
th1
Hold time, SCLK falling to data valid(2)
ns
VDD > 5 V
4
VDD = 3 V
9
15
td3
Delay time, 16th SCLK falling edge to SDO 3-state
ns
VDD = 5 V
8
11
VDD = 3 V
10
tw1
Pulse duration, CS
ns
VDD = 5 V
10
VDD = 3 V
9
15
td4
Delay time, CS high to SDO 3-state,
ns
VDD = 5 V
8
11
VDD = 3 V
0.45 × tSCLK
twH
Pulse duration, SCLK high
ns
VDD = 5 V
0.45 × tSCLK
VDD = 3 V
0.45 × tSCLK
twL
Pulse duration, SCLK low
ns
VDD = 5 V
0.45 × tSCLK
(1)
3-V Specifications apply from 2.7 V to 3.6 V, and 5-V specifications apply from 4.5 V to 5.5 V.
(2)
With 10-pf load.
4
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS7883
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