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参数资料
| 型号： | ADS8412IPFBTG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP48 |
| 封装： | GREEN, PLASTIC, TQFP-48 |
| 文件页数： | 15/29页 |
| 文件大小： | 1018K |
| 代理商： | ADS8412IPFBTG4 |
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RESET
POWER-ON INITIALIZATION
ADS8412
SLAS384A – JUNE 2003 – REVISED DECEMBER 2004
Table 1. Ideal Input Voltages and Output Codes
DIGITAL OUTPUT – TWOS COMPLEMENT
DESCRIPTION
ANALOG VALUE
BINARY CODE
HEX CODE
Full Scale Range
2(+Vref)
Least significant bit (LSB)
2(+Vref)/65536
+Full scale
(+Vref) – 1 LSB
0111 1111 1111 1111
7FFF
Midscale
0 V
0000 0000 0000 0000
0000
Midscale – 1 LSB
0 V – 1 LSB
1111 1111 1111 1111
FFFF
–Full scale
(–Vref)
1000 0000 0000 0000
8000
The output data is a full 16-bit word (D15-D0) on DB15-DB0 pins (MSB-LSB) if BYTE is low.
The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB15-DB8. In this
case two reads are necessary: the first as before, leaving BYTE low and reading the 8 most significant bits on
pins DB15-DB8, then bringing BYTE high. When BYTE is high, the low bits (D7-D0) appears on pins DB15-D8.
These multiword read operations can be done with multiple active RD (toggling) or with RD tied low for simplicity.
Table 2. Conversion Data Readout
DATA READ OUT
BYTE
DB15–DB8 Pins
DB7–DB0 Pins
High
D7–D0
All one's
Low
D15–D8
D7–D0
RESET is an asynchronous active low input signal (that works independantly of CS). Minimum RESET low time
is 25 ns. Current conversion will be aborted no later than 50 ns after the converter is in the reset mode. In
addition, all output latches are cleared (set to zero's) after RESET. The converter goes back to normal operation
mode no later than 20 ns after RESET input is brought high.
The converter starts the first sampling period 20 ns after the rising edge of RESET. Any sampling period except
for the one immediately after a RESET is started with the falling edge of the previous BUSY signal or the falling
edge of CS, whichever is later.
Another way to reset the device is through the use of the combination of CS and CONVST. This is useful when
the dedicated RESET pin is tied to the system reset but there is a need to abort only the conversion in a specific
converter. Since the BUSY signal is held high during the conversion, either one of these conditions triggers an
internal self-clear reset to the converter just the same as a reset via the dedicated RESET pin. The reset does
not have to be cleared as for the dedicated RESET pin. A reset can be started with either of the two following
steps.
Issue a CONVST when CS is low and a conversion is in progress. The falling edge of CONVST must satisfy
the timing as specified by the timing parameter tsu(AB) mentioned in the timing characteristics table to ensure
a reset. The falling edge of CONVST starts a reset. Timing is the same as a reset using the dedicated
RESET pin except the instance of the falling edge is replaced by the falling edge of CONVST.
Issue a CS while a conversion is in progress. The falling edge of CS must satisfy the timing as specified by
the timing parameter tsu(AB) mentioned in the timing characteristics table to ensure a reset. The falling edge of
CONVST starts a reset. The falling edge of CS causes a reset. Timing is the same as a reset using the
dedicated RESET pin except the instance of the falling edge is replaced by the falling edge of CS.
RESET is not required after power on. An internal power-on reset circuit generates the reset. To ensure that all
of the registers are cleared, three conversion cycles must be given to the converter after power on.
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