Rev. C
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Page 18 of 60
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January 2013
ELECTRICAL CHARACTERISTICS
Parameter Description
Test Conditions
Min
Max
Unit
VOH
High Level Output Voltag
e1@ VDDEXT = Min, IOH = –2.0 mA 2.4
V
VOL
Low Level Output Voltag
e1@ VDDEXT = Min, IOL = 4.0 mA 0.4
V
IIH
@ VDDEXT = Max, VIN = VDDEXT Max
10
μA
IIL
@ VDDEXT = Max, VIN = 0 V
10
μA
IIHC
CLKIN High Level Input Curren
t5@ VDDEXT = Max, VIN = VDDEXT Max
35
μA
IILC
CLKIN Low Level Input Current
5@ VDDEXT = Max, VIN = 0 V
35
μA
IIKH
Keeper High Load Curren
t6@ VDDEXT = Max, VIN = 2.0 V
–250
–100
μA
IIKL
@ VDDEXT = Max, VIN = 0.8 V
50
200
μA
IIKH-OD
@ VDDEXT = Max
–300
μA
IIKL-OD
@ VDDEXT = Max
300
μA
IILPU
Low Level Input Current Pull-U
p4@ VDDEXT = Max, VIN = 0 V
350
μA
IOZH
@ VDDEXT = Max, VIN = VDDEXT Max
10
μA
IOZL
@ VDDEXT = Max, VIN = 0 V
10
μA
IOZLPU1
Three-State Leakage Current Pull-Up1
10@ VDDEXT = Max, VIN = 0 V
500
μA
IOZLPU2
Three-State Leakage Current Pull-Up2
11@ VDDEXT = Max, VIN = 0 V
350
μA
IOZHPD1
Three-State Leakage Current Pull-Down1
12@ VDDEXT = Max, VIN = VDDEXT Max
350
μA
IOZHPD2
Three-State Leakage Current Pull-Down2
13@ VDDEXT = Max, VIN = VDDEXT Max
500
μA
IDD-INPEAK
tCCLK = 9.0 ns, VDDINT = Max
tCCLK = 10.0 ns, VDDINT = Max
965
900
mA
IDD-INHIGH
tCCLK = 9.0 ns, VDDINT = Max
tCCLK = 10.0 ns, VDDINT = Max
700
650
mA
IDD-INLOW
tCCLK = 9.0 ns, VDDINT = Max
tCCLK = 10.0 ns, VDDINT = Max
535
500
mA
IDD-IDLE
tCCLK = 9.0 ns, VDDINT = Max
tCCLK = 10.0 ns, VDDINT = Max
425
400
mA
AIDD
Supply Current (Analo
g)19@ AVDD = Max
10
mA
CIN
fIN = 1 MHz, TCASE = 25°C, VIN = 1.8 V
4.7
pF
1 Applies to output and bidirectional pins: DATA47–16, ADDR23–0, MS3–0, RD, WR, ACK, DQM, FLAG11–0, HBG, REDY, DMAG1, DMAG2,
BR6–1, BMSTR, PA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE, SDA10, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI, MISO, BMS, SDCLKx, SDCKE, EMU, XTAL,
TDO, CLKOUT, TIMEXP, RSTOUT.
3 Applies to input pins: DATA47–16, ADDR23–0, MS3–0, SBTS, IRQ2–0, FLAG11–0, HBG, HBR, CS, BR6–1, ID2–0, RPBA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE,
SDCLK0, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI, MISO, SPIDS, EBOOT, LBOOT, BMS, SDCKE, CLK_CFGx, CLKDBL, TCK, RESET, CLKIN.
4 Applies to input pins with 20 k internal pull-ups: RD, WR, ACK, DMAR1, DMAR2, PA, TRST, TMS, TDI.
5 Applies to CLKIN only.
6 Applies to all pins with keeper latches: ADDR23–0, DATA47–0, MS3–0, BRST, CLKOUT.
7 Current required to switch from kept high to low or from kept low to high.
8 Characterized, but not tested.
9 Applies to three-statable pins: DATA47–16, ADDR23–0, MS3–0, CLKOUT, FLAG11–0, REDY, HBG, BMS, BR6–1, RAS, CAS, SDWE, DQM, SDCLKx, SDCKE, SDA10,
BRST.
10Applies to three-statable pins with 20 kpull-ups: RD, WR, DMAG1, DMAG2, PA.
11Applies to three-statable pins with 50 k internal pull-ups: DxA, DxB, SCLKx, SPICLK., EMU, MISO, MOSI.
12Applies to three-statable pins with 50 k internal pull-downs: LxDAT7–0 (below Revision1.2), LxCLK, LxACK. Use IOZHPD2 for Rev. 1.2 and higher.
13Applies to three-statable pins with 20 k internal pull-downs: LxDAT7-0 (Revision 1.2 and higher).
14The test program used to measure I
DDINPEAK represents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power
15Current numbers are for V
DDINT and AVDD supplies combined.
19Characterized, but not tested.
20Applies to all signal pins.
21Guaranteed, but not tested.