- 您现在的位置：买卖IC网 > PDF目录19384 > ADSP-21161NKCA-100 (Analog Devices Inc)IC DSP CONTROLLER 32BIT 225MBGA PDF资料下载
参数资料
| 型号： | ADSP-21161NKCA-100 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/60页 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 32BIT 225MBGA |
| 产品培训模块： | SHARC Processor Overview |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | 主机接口，连接端口，串行端口 |
| 时钟速率： | 100MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 128kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.80V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 225-BGA，CSPBGA |
| 供应商设备封装： | 225-CSPBGA（17x17） |
| 包装： | 托盘 |
| 其它名称： | ADSP-21161NKCA100 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页当前第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页
Rev. C
|
Page 22 of 60
|
January 2013
Power-Up Sequencing — Silicon Revision 1.2 and Greater
The timing requirements for DSP startup are given in Table 10.
During the power-up sequence of the DSP, differences in the
ramp-up rates and activation time between the two supplies can
cause current to flow in the I/O ESD protection circuitry. To
prevent damage to the ESD diode protection circuitry, Analog
Devices recommends including a bootstrap Schottky diode.
The bootstrap Schottky diode is connected between the 1.8 V
and 3.3 V power supplies as shown in Figure 9. It protects the
ADSP-21161N from partially powering the 3.3 V supply.
Including a Schottky diode will shorten the delay between
the supply ramps and thus prevent damage to the ESD diode
protection circuitry. With this technique, if the 1.8 V rail rises
ahead of the 3.3 V rail, the Schottky diode pulls the 3.3 V rail
along with the 1.8 V rail.
Figure 9. Dual Voltage Schottky Diode
3.3V I/O
VOLTAGE
REGULATOR
1.8VCORE
VOLTAGE
REGULATOR
VDDEXT
VDDINT
ADSP-21161N
DC INPUT
SOURCE
Table 10. Power-Up Sequencing Silicon Revision 1.2 and Greater (DSP Startup)
Parameter
Min
Max
Unit
Timing Requirements
tRSTVDD
RESET Low Before VDDINT/VDDEXT on
0
ns
tIVDDEVDD
VDDINT on Before VDDEXT
–50
+200
ms
tCLKVDD
0200
ms
tCLKRST
CLKIN Valid Before RESET Deasserted
10
μs
tPLLRST
PLL Control Setup Before RESET Deasserted
20
μs
tWRST
Subsequent RESET Low Pulsewidth
4tCK
ns
Switching Requirements
tCORERST
DSP core reset deasserted after RESET deasserted
4080tCK
1 Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.8 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
depending on the design of the power supply subsystem.
2 Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to the crystal oscillator manufacturer's data sheet for start-up time.
Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3 Based on CLKIN cycles.
4 Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and
propagate default states at all I/O pins.
5 The 4080 cycle count depends on tSRST specification in Table 12. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in
4081 cycles maximum.
Figure 10. Power-Up Sequencing for Silicon Revision 1.2 and Greater (DSP Startup)
RESET
RSTOUT
CLKDBL
CLK_CFG1-0
CLKIN
tRSTVDD
VDDEXT
VDDINT
tPLLRST
tCLKRST
tCLKVDD
tIVDDEVDD
tCORERST
相关PDF资料 |
PDF描述 |
|---|---|
| JWS1505/A | POWER SUP 150W 5V 30A ENCLOSED |
| RMC44DRYN | CONN EDGECARD 88POS DIP .100 SLD |
| ECM12DTBD-S189 | CONN EDGECARD 24POS R/A .156 SLD |
| RSC44DRYH | CONN EDGECARD 88POS DIP .100 SLD |
| VI-B1V-CV-F1 | CONVERTER MOD DC/DC 5.8V 150W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-21161NKCA-100Z | 制造商:Analog Devices 功能描述: |
| ADSP-21161NKCAZ100 | 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-21161NYCAZ110 | 功能描述:IC DSP CONTROLLER 32BIT 225BGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-21261 | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Embedded Processor |
| ADSP-21261SKBC-150 | 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 150MHz 150MIPS 136-Pin CSP-BGA 制造商:Rochester Electronics LLC 功能描述:150 MHZ, 32BIT DSP PROCESSOR. - Bulk |
发布紧急采购，3分钟左右您将得到回复。