参数资料
型号: ADSP-21364KSWZ-1AA
厂商: Analog Devices Inc
文件页数: 41/60页
文件大小: 0K
描述: IC DSP 32BIT 333MHZ EPAD 144LQFP
产品培训模块: SHARC Processor Overview
标准包装: 1
系列: SHARC®
类型: 浮点
接口: DAI,SPI
时钟速率: 333MHz
非易失内存: ROM(512 kB)
芯片上RAM: 384kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.20V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 144-LQFP 裸露焊盘
供应商设备封装: 144-LQFP(20x20)
包装: 托盘
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
S/PDIF Receiver
The following section describes timing as it relates to the
S/PDIF receiver. This feature is not available on the
ADSP-21363 processors.
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL
(digital PLL) generates the 512 × FS clock.
Table 38. S/PDIF Receiver Output Timing (Internal Digital PLL Mode)
Parameter
Min
Max
Unit
Switching Characteristics
t DFSI
t HOFSI
t DDTI
t HDTI
t SCLKIW 1
Frame Sync Delay After Serial Clock
Frame Sync Hold After Serial Clock
Transmit Data Delay After Serial Clock
Transmit Data Hold After Serial Clock
Transmit Serial Clock Width
–2
–2
38
5
5
ns
ns
ns
ns
ns
1
Serial clock frequency is 64 ×FS where FS = the frequency of frame sync.
DRIVE EDGE
SAMPLE EDGE
t SCLKIW
DAI_P20–1
(SCLK)
t DFSI
t HOFSI
DAI_P20–1
(FS)
t DDTI
t HDTI
DAI_P20–1
(DATA CHANNEL
A/B)
Figure 33. S/PDIF Receiver Internal Digital PLL Mode Timing
Rev. J |
Page 41 of 60 |
July 2013
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