- 您现在的位置：买卖IC网 > PDF目录19467 > ADSP-21469KBCZ-3 (Analog Devices Inc)IC DSP 32/40BIT 400MHZ 324BGA PDF资料下载
参数资料
| 型号： | ADSP-21469KBCZ-3 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/72页 |
| 文件大小： | 0K |
| 描述： | IC DSP 32/40BIT 400MHZ 324BGA |
| 产品变化通告： | Pin Function Change 08/Mar/2012 |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | DAI，DPI，EBI/EMI，I²C，SCI，SPI，SSP，UART/USART |
| 时钟速率： | 400MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 5Mb |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.05V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 324-BGA，CSPBGA |
| 供应商设备封装： | 324-CSPBGA |
| 包装： | 托盘 |
第1页第2页第3页第4页当前第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页
ADSP-21469
Rev. 0
|
Page 13 of 72
|
June 2010
DDR2_ADDR15–0
O/T
High-Z/driven
low
DDR2 Address. DDR2 address pins.
DDR2_BA2-0
O/T
High-Z/driven
low
DDR2 Bank Address Input. Defines which internal bank an ACTIVATE, READ, WRITE,
or PRECHARGE command is being applied to. BA2–0define which mode registers,
including MR, EMR, EMR(2), and EMR(3) are loaded during the LOAD MODE REGISTER
command.
DDR2_CAS
O/T
High-Z/driven
high
DDR2 Column Address Strobe. Connect to DDR2_CAS pin; in conjunction with
other DDR2 command pins, defines the operation for the DDR2 to perform.
DDR2_CKE
O/T
High-Z/driven
low
DDR2 Clock Enable Output to DDR2. Active high signal. Connect to DDR2 CKE
signal.
DDR2_CS3-0
O/T
High-Z/driven
high
DDR2 Chip Select. All commands are masked when DDR2_CS3-0 is driven high.
DDR2_CS3-0 are decoded memory address lines. Each DDR2_CS3-0 line selects the
corresponding external bank.
DDR2_DATA15-0
I/O/T
High-Z
DDR2 Data In/Out. Connect to corresponding DDR2_DATA pins.
DDR2_DM1-0
O/T
High-Z/driven
high
DDR2 Input Data Mask. Mask for the DDR2 write data if driven high. Sampled on
both edges of DDR2_DQS at DDR2 side. DM0 corresponds to DDR2_DATA 7–0 and
DM1 corresponds to DDR2_DATA15–8.
DDR2_DQS1-0
I/O/T (Differential)
High-Z
Data Strobe. Output with Write Data. Input with Read Data. DQS0 corresponds to
DDR2_DATA 7–0 and DQS1 corresponds to DDR2_DATA 15–8. Based on software
control via the DDR2CTL3 register, this pin can be single-ended or differential.
DDR2_RAS
O/T
High-Z/driven
high
DDR2 Row Address Strobe. Connect to DDR2_RAS pin; in conjunction with other
DDR2 command pins, defines the operation for the DDR2 to perform.
DDR2_WE
O/T
High-Z/driven
high
DDR2 Write Enable. Connect to DDR2_WE pin; in conjunction with other DDR2
command pins, defines the operation for the DDR2 to perform.
DDR2_CLK0,
DDR2_CLK1,
DDR2_CLK1
O/T (Differential)
High-Z/driven
low
DDR2 Memory Clocks. Two differential outputs available via software control
(DDR2CTL0 register). Free running, minimum frequency not guaranteed during reset.
DDR2_ODT
O/T
High-Z/driven
low
DDR2 On Die Termination. ODT pin when driven high (along with other require-
ments) enables the DDR2 termination resistances. ODT is enabled/disabled
regardless of read or write commands.
Table 9. Pin Descriptions (Continued)
Name
Type
State During/
After Reset
Description
The following symbols appear in the Type column of Table 9: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,
O/D = open-drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels.
To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be
enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 k
–63 k. The range
of an ipd resistor can be between 31 k
–85 k.
In this table, the DDR2 pins are SSTL18 compliant. All other pins are LVTTL compliant.
相关PDF资料 |
PDF描述 |
|---|---|
| DS1620S+ | IC THERMOMETER/STAT DIG 8-SOIC |
| XC2C384-10FGG324I | IC CR-II CPLD 384MCELL 324-FBGA |
| MAX31855JASA+ | IC CONV THERMOCOUPLE-DGTL 8SOIC |
| VE-B1N-CW-B1 | CONVERTER MOD DC/DC 18.5V 100W |
| ADSP-21489BSWZ-4B | IC CCD SIGNAL PROCESSOR 176LQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-21469KBCZ-4 | 功能描述:IC DSP 32/40BIT 450MHZ 324BGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP21469KBCZENG | 制造商:Analog Devices 功能描述: |
| ADSP-21469KBCZ-ENG | 制造商:Analog Devices 功能描述:FXD PT PROC - Trays |
| ADSP-21469KBCZ-X | 制造商:Analog Devices 功能描述:FXD PT PROC - Trays |
| ADSP-21469KBZ-EN | 制造商:Analog Devices 功能描述: |
发布紧急采购，3分钟左右您将得到回复。