参数资料
型号: ADSP-2171BSTZ-133
厂商: Analog Devices Inc
文件页数: 29/52页
文件大小: 0K
描述: IC DSP CONTROLLER 16BIT 128TQFP
产品变化通告: Product Discontinuance 27/Oct/2011
Mold Change 11/Jul/2012
标准包装: 1
系列: ADSP-21xx
类型: 定点
接口: 主机接口,串行端口
时钟速率: 33MHz
非易失内存: 外部
芯片上RAM: 10kB
电压 - 输入/输出: 5.00V
电压 - 核心: 5.00V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 128-LQFP
供应商设备封装: 128-TQFP(14x20)
包装: 托盘
ADSP-2171/ADSP-2172/ADSP-2173
REV. A
–35–
ADSP-2173
Parameter
Min
Max
Unit
Bus Request/Grant
Timing Requirement:
tBH
BR
Hold after CLKOUT High
1
0.25tCK + 2
ns
tBS
BR
Setup before CLKOUT Low
1
0.25tCK + 22
ns
Switching Characteristic:
tSD
CLKOUT High to DMS, PMS, BMS,
0.25tCK + 16
ns
RD
, WR Disable
tSDB
DMS
, PMS, BMS, RD, WR
Disable to BG Low
0
ns
tSE
BG
High to DMS, PMS, BMS,
RD
, WR Enable
0
ns
tSEC
DMS
, PMS, BMS, RD, WR
Enable to CLKOUT High
0.25tCK – 10
ns
tSDBH
DMS
, PMS, BMS, RD, WR
Disable to BGH Low
2
0ns
tSEH
BGH
High to DMS, PMS, BMS,
RD
, WR Enable
2
0ns
NOTES
1BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized
on the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.
2BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
t
BS
BR
t
BH
CLKOUT
PMS, DMS
BMS, RD
WR
BG
CLKOUT
t
SD
t
SDB
t
SE
t
SEC
tSDBH
BGH
tSEH
Figure 26. Bus Request–Bus Grant
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