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| 型号： | ADSP-2171BSTZ-133 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 39/52页 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 128TQFP |
| 产品变化通告： | Product Discontinuance 27/Oct/2011 Mold Change 11/Jul/2012 |
| 标准包装： | 1 |
| 系列： | ADSP-21xx |
| 类型： | 定点 |
| 接口： | 主机接口，串行端口 |
| 时钟速率： | 33MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 10kB |
| 电压 - 输入/输出： | 5.00V |
| 电压 - 核心： | 5.00V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 托盘 |
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REV. A
–44–
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2173
CAPACITIVE LOADING
Figures 35 and 36 show the capacitive loading characteristics of
the ADSP-2173.
16
8
25
12
28
20
24
150
125
100
75
50
V
DD = 3.3 V
C
L – pF
RISE
TIME
(0.4
V
–
2.4
V)
–
ns
Figure 35. Typical Output Rise Time vs. Load Capacitance,
CL (at Maximum Ambient Operating Temperature)
NOMINAL
-2
25
+4
+2
+8
+10
+12
150
125
100
75
50
+14
VALID
OUTPUT
DELAY
OR
HOLD
–
ns
C
L – pF
Figure 36. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating
Temperature)
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured out-
put high or low voltage to a high impedance state. The output
disable time (tDIS) is the difference of tMEASURED and tDECAY, as
shown in the Output Enable/Disable diagram. The time is the
interval from when a reference signal reaches a high or low volt-
age level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage. The decay time,
tDECAY, is dependent on the capacitative load, CL, and the cur-
rent load, iL, on the output pin. It can be approximated by the
following equation:
t
DECAY =
C
L 0.5 V
i
L
from which
t
DIS = t MEASURED – tDECAY
is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.
INPUT
OUTPUT
V
DD
2
V
DD
2
Figure 37. Voltage Reference Levels for AC Measure-
ments (Except Output Enable/Disable)
Output Enable Time
Output pins are considered to be enabled when that have made
a transition from a high-impedance state to when they start driv-
ing. The output enable time (tENA) is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram. If multiple pins (such as
the data bus) are enabled, the measurement value is that of the
first pin to start driving.
2.0V
1.0V
t
ENA
REFERENCE
SIGNAL
OUTPUT
t
DECAY
VOH
(MEASURED)
OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
t
DIS
t
MEASURED
VOL
(MEASURED)
VOH (MEASURED) – 0.5V
VOL (MEASURED) +0.5V
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
VOH
(MEASURED)
VOL
(MEASURED)
Figure 38. Output Enable/Disable
TO
OUTPUT
PIN
50pF
I
OH
I
OL
V
DD
2
Figure 39. Equivalent Device Loading for AC Measure-
ments (Including All Fixtures)
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| ADSP-2171KS-104 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 26MHz 26MIPS 128-Pin PQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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