参数资料
型号: ADSP-2186MKSTZ300R
厂商: Analog Devices Inc
文件页数: 18/40页
文件大小: 0K
描述: IC DSP CONTROLLER 16BIT 100LQFP
标准包装: 1
系列: ADSP-21xx
类型: 定点
接口: 主机接口,串行端口
时钟速率: 75MHz
非易失内存: 外部
芯片上RAM: 40kB
电压 - 输入/输出: 3.30V
电压 - 核心: 2.50V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 100-LQFP
供应商设备封装: 100-LQFP(14x14)
包装: 标准包装
其它名称: ADSP-2186MKSTZ300RDKR
REV. 0
ADSP-2186M
–25–
Parameter
Min
Max
Unit
Bus Request–Bus Grant
Timing Requirements:
tBH
BR Hold after CLKOUT High1
0.25tCK + 2
ns
tBS
BR Setup before CLKOUT Low1
0.25tCK + 10
ns
Switching Characteristics:
tSD
CLKOUT High to
xMS, RD, WR Disable
0.25tCK + 8
ns
tSDB
xMS, RD, WR Disable to BG Low
0
ns
tSE
BG High to xMS, RD, WR Enable
0
ns
tSEC
xMS, RD, WR Enable to CLKOUT High
0.25tCK – 3ns
tSDBH
xMS, RD, WR Disable to BGH Low2
0ns
tSEH
BGH High to xMS, RD, WR Enable2
0ns
NOTES
xMS = PMS, DMS, CMS, IOMS, BMS.
1
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-2100 Family User’s Manual for
BR/BG cycle relationships.
2
BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue.
CLKOUT
tSD
tSDB
tSE
tSEC
tSDBH
tSEH
tBS
BR
tBH
CLKOUT
PMS, DMS
BMS, RD
WR
BG
BGH
Figure 23. Bus Request–Bus Grant
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