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参数资料
| 型号： | ADSP-2191MKSTZ-160 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/48页 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 144LQFP |
| 标准包装： | 1 |
| 系列： | ADSP-21xx |
| 类型： | 定点 |
| 接口： | 主机接口，SPI，SSP，UART |
| 时钟速率： | 160MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 160kB |
| 电压 - 输入/输出： | 3.00V，3.30V |
| 电压 - 核心： | 2.50V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-LQFP |
| 供应商设备封装： | 144-LQFP（20x20） |
| 包装： | 托盘 |
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ADSP-2191M
–12–
REV. A
The OPMODE, BMODE1, and BMODE0 pins, sampled
during hardware reset, and three bits in the Reset Configuration
Register implement these modes:
Execute from memory external 16 bits—The memory
boot routine located in boot ROM memory space
executes a boot-stream-formatted program located at
address 0x010000 of boot memory space, packing 16-bit
external data into 24-bit internal data. The External Port
Interface is configured for the default clock multiplier
(128) and read waitstates (7).
Boot from EPROM—The EPROM boot routine located
in boot ROM memory space fetches a boot-stream-for-
matted program located at physical address 0x00 0000 of
boot memory space, packing 8- or 16-bit external data
into 24-bit internal data. The External Port Interface is
configured for the default clock multiplier (32) and read
waitstates (7).
Boot from Host—The (8- or 16-bit) Host downloads a
boot-stream-formatted program to internal or external
memory. The Host’s boot routine is located in internal
ROM memory space and uses the top 16 locations of
Page 0 program memory and the top 272 locations of
Page 0 data memory.
The internal boot ROM sets semaphore A (an IO register
within the Host port) and then polls until the semaphore
is reset. Once detected, the internal boot ROM will remap
the interrupt vector table to Page 0 internal memory and
jump to address 0x00 0000 internal memory. From the
point of view of the host interface, an external host has
full control of the DSP’s memory map. The Host has the
freedom to directly write internal memory, external
memory, and internal I/O memory space. The DSP core
execution is held off until the Host clears the semaphore
register. This strategy allows the maximum flexibility for
the Host to boot in the program and data code, by leaving
it up to the programmer.
Execute from memory external 8 bits (No Boot)—
Execution starts from Page 1 of external memory space,
packing either 8- or 16-bit external data into 24-bit
internal data. The External Port Interface is config-
ured for the default clock multiplier (128) and read
waitstates (7).
Boot from UART—Using an autobaud handshake
sequence, a boot-stream-formatted program is down-
loaded by the Host. The Host agent selects a baud rate
within the UART’s clocking capabilities. After a hardware
reset, the DSP’s UART expects a 0xAA character (eight
bits data, one start bit, one stop bit, no parity bit) on the
RXD pin to determine the bit rate; and then replies with
an OK string. Once the host receives this OK it downloads
the boot stream without further handshake.The UART
boot routine is located in internal ROM memory space
and uses the top 16 locations of Page 0 program memory
and the top 272 locations of Page 0 data memory.
Boot from SPI, up to 4K bits—The SPI0 port uses the
SPI0SEL1 (reconfigured PF2) output pin to select a
single serial EEPROM device, submits a read command
at address 0x00, and begins clocking consecutive data into
internal or external memory. Use only SPI-compatible
EEPROMs of
≤ 4K bit (12-bit address range). The SPI0
boot routine located in internal ROM memory space
executes a boot-stream-formatted program, using the top
16 locations of Page 0 program memory and the top 272
locations of Page 0 data memory. The SPI boot configu-
ration is SPIBAUD0 = 60 (decimal), CPHA = 1,
CPOL = 1, 8-bit data, and MSB first.
Boot from SPI, from >4K bits to 512K bits—The SPI0
port uses the SPI0SEL1 (re-configured PF2) output pin
to select a single serial EEPROM device, submits a read
command at address 0x00, and begins clocking consecu-
tive data into internal or external memory. Use only
SPI-compatible EEPROMs of
≥ 4K bit (16-bit address
range). The SPI0 boot routine, located in internal ROM
memory space, executes a boot-stream-formatted
program, using the top 16 locations of Page 0 program
memory and the top 272 locations of Page 0 data memory.
As indicated in Table 6, the OPMODE pin has a dual role, acting
as a boot mode select during reset and determining SPORT or
SPI operation at runtime. If the OPMODE pin at reset is the
opposite of what is needed in an application during runtime, the
application needs to set the OPMODE bit appropriately during
runtime prior to using the corresponding peripheral.
Bus Request and Bus Grant
The ADSP-2191M can relinquish control of the data and ad-
dress buses to an external device. When the external device
requires access to the bus, it asserts the bus request (
BR) signal.
The (
BR) signal is arbitrated with core and peripheral requests.
External Bus requests have the lowest priority. If no other internal
request is pending, the external bus request will be granted.
Table 6. Select Boot Mode (OPMODE, BMODE1, and
BMODE0)
OP
MODE
BMODE1
BMODE0
Function
0
Execute from external memory 16 bits
(No Boot)
0
1
Boot from EPROM
0
1
0
Boot from Host
0
1
Reserved
1
0
Execute from external memory 8 bits
(No Boot)
1
0
1
Boot from UART
1
0
Boot from SPI, up to 4K bits
1
Boot from SPI, >4K bits up to
512K bits
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