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参数资料
型号： ADSP-BF547BBCZ-5A
厂商： ANALOG DEVICES INC
元件分类： 数字信号处理
英文描述： 533 MHz Blackfin Embedded Processor: ADSP-BF547BBCZ-5A Temp Range: –40°C to +85°C Package: 400-Ball CSP_BGA BC-400-1
中文描述： 16-BIT, 50 MHz, OTHER DSP, PBGA400
封装： 17 X 17 MM, ROHS COMPLIANT, CSBGA-400
文件页数： 37/100页
文件大小： 3095K
代理商： ADSP-BF547BBCZ-5A
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Rev. D
|
Page 41 of 100
|
May 2011
TIMING SPECIFICATIONS
Timing specifications are detailed in this section.
Clock and Reset Timing
Table 24 and Figure 10 describe Clock Input and Reset Timing.
Table 25 and Figure 11 describe Clock Out Timing.
Table 24. Clock Input and Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
tCKIN
CLKIN Period1, 2, 3, 4
20.0
100.0
ns
tCKINL
CLKIN Low Pulse2
8.0
ns
tCKINH
CLKIN High Pulse2
8.0
ns
tBUFDLAY
CLKIN to CLKBUF Delay
10
ns
tWRST
RESET Asserted Pulsewidth Low
5
11 tCKIN
ns
tRHWFT
RESET High to First HWAIT/HWAITA Transition (Boot Host Wait Mode)
6, 7, 8, 9 6100 t
CKIN + 7900 tSCLK
ns
tRHWFT
RESET High to First HWAIT/HWAITA Transition (Reset Output Mode)7, 10, 11
6100 tCKIN
7000 tCKIN
ns
1 Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed f
VCO, fCCLK, and fSCLK settings discussed in Table 15 and Table 12 on Page 34.
2 Applies to PLL bypass mode and PLL non-bypass mode.
3 CLKIN frequency and duty cycle must not change on the fly.
4 If the DF bit in the PLL_CTL register is set, then the maximum t
CKIN period is 50 ns.
5 Applies after power-up sequence is complete. See Table 26 and Figure 12 for more information about power-up reset timing.
6 Maximum value not specified due to variation resulting from boot mode selection and OTP memory programming.
7 Values specified assume no invalidation preboot settings in OTP page PBS00L. Invalidating a PBS set will increase the value by 1875 t
CKIN (typically).
8 Applies only to boot modes BMODE=1, 2, 4, 6, 7, 10, 11, 14, 15.
9 Use default t
SCLK value unless PLL is reprogrammed during preboot. In case of PLL reprogramming use the new tSCLK value and add PLL_LOCKCNT settle time.
10When enabled by OTP_RESETOUT_HWAIT bit. If regular HWAIT is not required in an application, the OTP_RESETOUT_HWAIT bit in the same page instructs the
HWAIT or HWAITA to simulate reset output functionality. Then an external resistor is expected to pull the signal to the reset level, as the pin itself is in high performance
mode during reset.
11Variances are mainly dominated by PLL programming instructions in PBS00L page and boot code differences between silicon revisions. The earlier is bypassed in boot
mode BMODE = 0. Maximum value assumes PLL programming instructions do not cause the SCLK frequency to decrease.
Figure 10. Clock and Reset Timing
CLKIN
tWRST
tCKIN
tCKINL
tCKINH
tBUFDLAY
RESET
CLKBUF
HWAIT (A)
tRHWFT
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