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| 型号： | ADSP-TS201SYBP-050 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/48页 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR 500MHZ 576-SBGA |
| 标准包装： | 1 |
| 系列： | TigerSHARC® |
| 类型： | 定点/浮点 |
| 接口： | 主机接口，连接端口，多处理器 |
| 时钟速率： | 500MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 3MB |
| 电压 - 输入/输出： | 2.50V |
| 电压 - 核心： | 1.05V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 576-BBGA 裸露焊盘 |
| 供应商设备封装： | 576-BGA-ED（25x25） |
| 包装： | 托盘 |
| 配用： | ADZS-TS201S-EZLITE-ND - KIT LITE EVAL FOR ADSP-TS201S |
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Rev. C
|
Page 16 of 48
|
December 2006
ADSP-TS201S
Table 8. Pin Definitions—External Port SDRAM Controller
Signal
Type
Term
Description
MSSD3–0
I/O/T
(pu_0)
nc
Memory Select SDRAM. MSSD0, MSSD1, MSSD2, or MSSD3 is asserted whenever the
DSP accesses SDRAM memory space. MSSD3–0 are decoded memory address pins
that are asserted whenever the DSP issues an SDRAM command cycle (access to
ADDR31:30 = 0b01—except reserved spaces shown in Figure 3 on Page 6). In a multi-
processor system, the master DSP drives MSSD3–0.
RAS
I/O/T
(pu_0)
nc
Row Address Select. When sampled low, RAS indicates that a row address is valid in
a read or write of SDRAM. In other SDRAM accesses, it defines the type of operation
to execute according to SDRAM specification.
CAS
I/O/T
(pu_0)
nc
Column Address Select. When sampled low, CAS indicates that a column address is
valid in a read or write of SDRAM. In other SDRAM accesses, it defines the type of
operation to execute according to the SDRAM specification.
LDQM
O/T
(pu_0)
nc
Low Word SDRAM Data Mask. When sampled high, three-states the SDRAM DQ
buffers. LDQM is valid on SDRAM transactions when CAS is asserted, and inactive on
read transactions. On write transactions, LDQM is active when accessing an odd
address word on a 64-bit memory bus to disable the write of the low word.
HDQM
O/T
(pu_0)
nc
High Word SDRAM Data Mask. When sampled high, three-states the SDRAM DQ
buffers. HDQM is valid on SDRAM transactions when CAS is asserted, and inactive on
read transactions. On write transactions, HDQM is active when accessing an even
address in word accesses or when memory is configured for a 32-bit bus to disable
the write of the high word.
SDA10
O/T
(pu_0)
nc
SDRAM Address Bit 10. Separate A10 signals enable SDRAM refresh operation while
the DSP executes non-SDRAM transactions.
SDCKE
I/O/T
(pu_m/
pd_m)
nc
SDRAM Clock Enable. Activates the SDRAM clock for SDRAM self-refresh or suspend
modes. A slave DSP in a multiprocessor system does not have the pull-up or pull-
down. A master DSP (or ID = 0 in a single processor system) has a pull-up before
granting the bus to the host, except when the SDRAM is put in self refresh mode. In
self refresh mode, the master has a pull-down before granting the bus to the host.
SDWE
I/O/T
(pu_0)
nc
SDRAM Write Enable. When sampled low while CAS is active, SDWE indicates an
SDRAM write access. When sampled high while CAS is active, SDWE indicates an
SDRAM read access. In other SDRAM accesses, SDWE defines the type of operation to
execute according to SDRAM specification.
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5k
Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal
pull-up 500
Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad
= internal pull-up 40 k
Ω. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k
Ω to VSS; epu = external pull-up approx-
imately 5 k
Ω to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS
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相关代理商/技术参数 |
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| ADSP-TS201SYBPZ050 | 功能描述:IC PROCESSOR 500MHZ 576-SBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:TigerSHARC® 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-TS202SABP-050 | 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 500MHz 500MIPS 576-Pin TEBGA 制造商:Analog Devices 功能描述:DSP FLOATING PT 32BIT 500MHZ 500MIPS 576PIN TEBGA - Trays |
| ADSP-TS202SABP-05X | 制造商:Analog Devices 功能描述: |
| ADSP-TS202SABP-X | 制造商:Analog Devices 功能描述: |
| ADSP-TS202SABPZ050 | 功能描述:IC PROCESSOR 500MHZ 576BGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:TigerSHARC® 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
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