参数资料
型号: ADT7318ARU
厂商: ANALOG DEVICES INC
元件分类: 温度/湿度传感器
英文描述: DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 3Cel, RECTANGULAR, SURFACE MOUNT
封装: QSOP-16
文件页数: 18/24页
文件大小: 279K
代理商: ADT7318ARU
ADT7316/7317/7318
–3–
REV. PrH
Preliminary Technical Data
PRELIMINARY TECHNICAL DATA
I
2CTIMINGCHARACTERISTICS7,8
Serial Clock Period, t1
2.5
s
Fast-Mode I
2C. See Figure 1
Data In Setup Time to SCL High, t2
Data Out Stable after SCL Low, t3
0
ns
See Figure 1
SDA Low Setup Time to SCL Low
(Start Condition), t4
50
ns
See Figure 1
SDA High Hold Time after SCL High
(Stop Condition), t5
50
ns
See Figure 1
SDA and SCL Fall Time, t6
90
ns
See Figure 1
SPI TIMING CHARACTERISTICS
9,10
CS to SCLK Setup Time, t
1
0
ns
See Figure 2
SCLK High Pulsewidth, t2
50
ns
See Figure 2
SCLK Low Pulse, t3
50
ns
See Figure 2
Data Access Time after
SCLK Falling edge, t4
11
35
ns
See Figure 2
Data Setup Time Prior
to SCLK Rising Edge, t5
20
ns
See Figure 2
Data Hold Time after
SCLK Rising Edge, t6
0
ns
See Figure 2
CS to SCLK Hold Time, t
7
0
ns
See Figure 2
CS to DOUT High Impedance
40
ns
See Figure 2
POWER REQUIREMENTS
VDD
2.7
5.5
V
IDD (Normal Mode)
9
0.85
1.3
m A
VIH = VDD and VIL = GND
IDD (Power Down Mode)
1
3
A
VDD = +4.5V to +5.5V, VIH=VDD and VIL=GND
0.5
1
A
VDD = +2.7V to +3.6V, VIH=VDD and VIL=GND
Power Dissipation
tbd
W
VDD = +2.7 V. Using Normal Mode
tbd
W
VDD = +2.7 V. Using Shutdown Mode
Notes:
1 See Terminology
2 Temperature ranges are as follows: B Version: -40°C to +125°C.
3 DC specifications tested with the outputs unloaded.
4 Linearity is tested using a reduced code range:; ADT7316 (code 115 to 4095); ADT7317 (code 28 to 1023); ADT7318 (code 8 to 255)
5 Guaranteed by Design and Characterization, not production tested
6 In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, V
REF=VDD
and "Offset plus Gain" Error must be positive.
7 The SDA & SCL timing is measured with the input filters turned on so as to meet the Fast-Mode I2C specification. Switching off the input filters improves the transfer
rate but has a negative affect on the EMC behaviour of the part.
8 Guaranteed by design. Not tested in production.
9 Guaranteed by design and characterization, not production tested.
10 All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD) and timed from a voltage level of 1.6 V.
11 Measured with the load circuit of Figure 3.
12 I
DD spec. is valid for all DAC codes. Interface inactive. All DACs active. Load currents excluded.
Specifications subject to change without notice.
Parameter
1
Min
Typ
M a x
Units
Conditions/Comments
t1
t4
t2
t
3
t5
SC L
SD A
DA T A IN
SD A
DA T A O U T
J$
Figure 1. Diagram for I2C Bus Timing
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