–16–
REV. PrH
Preliminary Technical Data
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
CONFIGURATION REGISTER 2
This Configuration Register is an 8-bit read/write register
that is used to set the operating modes of the ADT7316/
17/18. The 4 MSBs are used to set the operating modes,
see Table XX. D0, D1, D2 and D3 are used for factory
settings and must have zeros written to them during nor-
mal operation.
Table xx.
Configuration Register 2
D7
D6
D5
D4
D3
D2
D1
D0
G
Buf_AB
Buf_CD
Pol
AR
AI
N / A
0*
* Default settings at Power-up
Table xx.
Configuration Register 2 Settings
Bit
Function
D 7
Gain
This bit changes the output range of
all four DACs.
0 = Output range of 0 V to Vref
1 = Output range of 0 V to 2Vref
D 6
Buf_AB
This bit controls whether the internal
or external reference to DACs A and B
is buffered or unbuffered.
0 = Unbuffered Int/Ext Vref
1 = Buffered Int/Ext Vref
D 5
Buf_CD
This bit controls whether the internal
or external reference to DACs C and
D is buffered or unbuffered.
0 = Unbuffered Int/Ext Vref
1 = Buffered Int/Ext Vref
D 4
Polarity
This bit controls the output polarity of
pin 1 (ALERT/TI).
0 = Active low ALERT/TI
1 = Active high ALERT/TI
D 3
Alert Reset Reset the
ALERT/TI pin if set to 1.
The next temperature conversion will
have the ability to activate the
ALERT/TI function. The bit status is
not stored, thus this bit will be “0” if
read.
D 2
Auto
Setting this bit to a 1 enables the Ad-
dress Pointer to be auto-incremented
when reading from or writing to the
registers in Table xx.
0 = Auto-Increment disabled
1 = Auto-Increment enabled
DAC (
LDAC) MASK REGISTER
USE ??????
MASK REGISTER (R/W)
This register can be used to mask out any of the interrupts
that can cause
ALERT/TI to go active and can also mask
out the capability of the
LDAC signal to update the
DACs. Bit 4 is reserved and writing to this bit will have
no affect.
Table X.
Interrupt Mask Register
D7
D6
D5
D4
D3
D2
D1
D0
I H *
E H * Open*
0 *
LDAC*
* Default setting is 0.
Setting D5 to D7 to a 1 will mask out the interrupts rep-
resented by these bits. IH represents the interrupt caused
by Internal THIGH register. EH represents the interrupt
caused by External THIGH register. Open represents the
interrupt caused by an open circuit on D
+ and D-.
Table VII.
LDAC Register
Bits
Function
D 3
Enables/disables
LDAC to update DAC A
D 2
Enables/disables
LDAC to update DAC B
D 1
Enables/disables
LDAC to update DAC C
D 0
Enables/disables
LDAC to update DAC D
Setting D0 to D3 to a 1 disables the
LDAC. Example by
setting the register to a value of 1010 (0Ah), this disables
the
LDAC in updating DACs A and C.
INTERNAL TEMPERATURE VALUE REGISTER (8
MSBS)
This Internal Temperature Value Register is a 8-bit read-
only register which stores the temperature reading from
the internal temperature sensor in twos complement for-
mat. This 8 MSBs of the internal temperature reading is
stored in this register.
Table xx.
Internal Temperature Value Register (First
Read)
D7
D6
D5
D4
D3
D2
D1
D0
M S B
B8
B7
B6
B5
B4
B3
B2
INTERNAL TEMPERATURE VALUE REGISTER (2
LSBS)
This Internal Temperature Value Register is a 8-bit read-
only register which stores the temperature reading from
the internal temperature sensor in twos complement for-
mat. The 2 LSBs of the internal temperature reading is
stored in this register.
Table xx.
Internal Temperature Value Register (Second
Read)
D7
D6
D5
D4
D3
D2
D1
D0
B1
LSB
0