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| 型号： | ADT7476ARQZ-R7 |
| 厂商： | ON Semiconductor |
| 文件页数： | 52/65页 |
| 文件大小： | 0K |
| 描述： | IC REMOTE THERMAL CTLR 24-QSOP |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi QSOP 24ld Pkg (MSL) Change 17/Jun/2010 Product Discontinuation 30/Sept/2011 |
| 标准包装： | 1,000 |
| 系列： | dBCool® |
| 功能： | 风扇控制，温度监控器 |
| 传感器类型： | 内部和外部 |
| 感应温度： | -40°C ~ 125°C |
| 精确度： | ±2.5% |
| 拓扑： | ADC，比较器，风扇速度计数器，多路复用器，寄存器库 |
| 输出类型： | SMBus? |
| 输出警报： | 无 |
| 输出风扇： | 是 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 24-QSOP |
| 包装： | 带卷 (TR) |
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ADT7476
Table 59. REGISTER 0X42 ? INTERRUPT STATUS REGISTER 2 (POWER-ON DEFAULT = 0X00)
Bit No.
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Mnemonic
12 V/VC
OVT
FAN1
FAN2
FAN3
F4P
D1
D2
R/W
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
R/W
Read-only
Read-only
Read-only
Description
A 1 indicates that the 12 V high or low limit has been exceeded. This bit is cleared on a read
of the status register only if the error condition has subsided. If Pin 21 is configured as VID5,
this bit is the VID change bit. This bit is set when the levels on VID0 to VID5 are different
than they were 11 m s previously. This pin can be used to generate an SMBALERT whenever
the VID code changes.
OVT = 1 indicates that one of the THERM overtemperature limits has been exceeded. This
bit is cleared on a read of the status register when the temperature drops below
THERM ? T HYST .
FAN1 = 1 indicates that Fan 1 has dropped below minimum speed or has stalled. This bit is
not set when the PWM1 output is off.
FAN2 = 1 indicates that Fan 2 has dropped below minimum speed or has stalled. This bit is
not set when the PWM2 output is off.
FAN3 = 1 indicates that Fan 3 has dropped below minimum speed or has stalled. This bit is
not set when the PWM3 output is off.
When Pin 14 is programmed as a TACH4 input, F4P = 1 indicates that Fan 4 has dropped
below minimum speed or has stalled. This bit is not set when the PWM3 output is off.
When Pin 14 is programmed as the GPIO6 output, writing to this bit determines the logic
output of GPIO6. When GPIO6 is programmed as an input, this bit reflects the value read by
GPIO6.
If Pin 14 is configured as the THERM timer input for THERM monitoring, then this bit is set
when the THERM assertion time exceeds the limit programmed in the THERM timer limit
register (0x7A).
D1 = 1 indicates either an open or short circuit on the Thermal Diode 1 inputs.
D2 = 1 indicates either an open or short circuit on the Thermal Diode 2 inputs.
Table 60. REGISTER 0X43 ? VID/GPIO REGISTER (POWER-ON DEFAULT = 0X1F)
Bit No.
[4:0]
[5]
[6]
[7]
Mnemonic
VID[4:0]/
GPIO[4:0]
VID5
THLD
VIDSEL
R/W
R/W
R/W
R/W
R/W
Description
The VID[4:0] inputs from the CPU indicate the expected processor core voltage. On
powerup, these bits reflect the state of the VID pins, even if monitoring is not enabled. When
Bit 4 of Configuration Register 5 (0x7C) = 1, these bits become general-purpose outputs. The
state of these bits then reflects the state of the appropriate GPIO pin.
Reads VID5 from the CPU when Bit 7 = 1. If Bit 7 = 0, the VID5 bit always reads back 0
(power-on default).
Selects the input switching threshold for the VID inputs.
THLD = 0 selects a threshold of 1 V (V OL < 0.8 V, V IH > 1.7 V).
THLD = 1 lowers the switching threshold to 0.6 V (V OL < 0.4 V, V IH > 0.8 V).
VIDSEL = 0 configures Pin 21 as the 12 V measurement input (default).
Table 61. VOLTAGE LIMIT REGISTERS (Note 1)
Register Address
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2.5 V Low Limit
2.5 V High Limit
V CCP Low Limit
V CCP High Limit
V CC Low Limit
V CC High Limit
5.0 V Low Limit
5.0 V High Limit
12 V Low Limit
12 V High Limit
Description (Note 2)
Power-On Default
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
1. Setting the Configuration Register 1 Lock bit has no effect on these registers.
2. High limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low limits: An interrupt is generated when a value
is equal to or below its low limit ( ≤ comparison).
http://onsemi.com
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