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型号： ADUC7034BCPZ
厂商： Analog Devices Inc
文件页数： 25/136页
文件大小： 0K
描述： IC MCU FLASH 32K ANLG IO 48LFCSP
标准包装： 1
系列： MicroConverter® ADuC7xxx
核心处理器： ARM7
芯体尺寸： 16/32-位
速度： 20.48MHz
连通性： LIN，SPI，UART/USART
外围设备： POR，PSM，温度传感器，WDT
输入/输出数： 9
程序存储器容量： 32KB（16K x 16）
程序存储器类型： 闪存
RAM 容量： 1K x 32
电压 - 电源 (Vcc/Vdd)： 3.5 V ~ 18 V
数据转换器： A/D 2x16b
振荡器型： 内部
工作温度： -40°C ~ 115°C
封装/外壳： 48-VFQFN 裸露焊盘，CSP
包装： 托盘
ADuC7034
Rev. B | Page 120 of 136
Bit
Description
6
Mode of operation bit.
Set to 1 by user code to select BSD mode of operation.
Cleared to 0 by user code to select LIN mode of operation.
5
Enable compare interrupt bit.
Set to 1 by user code to generate an LHS interrupt (IRQEN[7]) when the value in LHSVAL0 (the LIN synchronization bit timer) equals
the value in the LHSCMP register. The LHS compare interrupt bit (LHSSTA[3]) is set when this interrupt occurs. This configuration
is used in BSD write mode to allow user code to correctly time the output pulse widths of BSD bits to be transmitted.
Cleared to 0 by user code to disable compare interrupts.
4
Enable stop interrupt.
Set to 1 by user code to generate an interrupt when a stop condition occurs.
Cleared to 0 by user code to disable interrupts when a stop condition occurs.
3
Enable start interrupt.
Set to 1 by user code to generate an interrupt when a start condition occurs.
Cleared to 0 by user code to disable interrupts when a start condition occurs.
2
LIN sync enable bit.
Set to 1 by user code to enable LHS functionality.
Cleared to 0 by user code to disable LHS functionality.
1
Edge counter clear bit.
Set to 1 by user code to clear the internal edge counters in the LHS peripheral.
Cleared automatically to 0 after a 15 μs delay.
0
LHS reset bit.
Set to 1 by user code to reset all LHS logic to default conditions.
Cleared automatically to 0 after a 15 μs delay.
1 In BSD mode, LHSCON0[6] is set to 1. Because of the finite propagation delay in the BSD transmit (from the MCU to the external pin) and receive (from the external pin
to the MCU) paths, user code must not switch between BSD write and read modes until the MCU confirms that the external BSD pin is deasserted. Failure to adhere to
this recommendation can result in the generation of an inadvertent break condition interrupt after user code switches from BSD write mode to BSD read mode. A stop
condition interrupt can be used to ensure that this scenario is avoided.
LIN Hardware Synchronization Control Register 1
Name:
LHSCON1
Address:
0xFFFF078C
Default Value:
0x32
Access:
Read/write
Function:
The LHS control register is an 8-bit register that is used in conjunction with the LHSCON0 register to configure the LIN
mode of operation.
Table 93. LHSCON1 MMR Bit Designations
Bit
Description
7 to 4
LIN stop edge count. These bits are set by user code to the number of falling or rising edges on which to stop the
internal LIN synchronization counter. The stop value of this counter can be read by user code via LHSVAL0. The type of
edge, either rising or falling, is configured by LHSCON0[7]. The default value of these bits is 0x3, which configures the
hardware to stop counting on the third falling edge. It should be noted that the first falling edge is considered to be the
falling edge at the start of the LIN break pulse.
3 to 0
LIN start edge count. These four bits are set by user code to the number of falling edges that must occur before the
internal LIN synchronization timer starts counting. The stop value of this counter can be read by user code via LHSVAL0.
The default value of these bits is 0x2, which configures the hardware to start counting on the second falling edge. Note
that the first falling edge is considered to be the falling edge at the start of the LIN break pulse.
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