参数资料
型号: ADUC7034BCPZ
厂商: Analog Devices Inc
文件页数: 57/136页
文件大小: 0K
描述: IC MCU FLASH 32K ANLG IO 48LFCSP
标准包装: 1
系列: MicroConverter® ADuC7xxx
核心处理器: ARM7
芯体尺寸: 16/32-位
速度: 20.48MHz
连通性: LIN,SPI,UART/USART
外围设备: POR,PSM,温度传感器,WDT
输入/输出数: 9
程序存储器容量: 32KB(16K x 16)
程序存储器类型: 闪存
RAM 容量: 1K x 32
电压 - 电源 (Vcc/Vdd): 3.5 V ~ 18 V
数据转换器: A/D 2x16b
振荡器型: 内部
工作温度: -40°C ~ 115°C
封装/外壳: 48-VFQFN 裸露焊盘,CSP
包装: 托盘
ADuC7034
Rev. B | Page 27 of 136
Command Sequence for Executing a Mass Erase
Given the significance of the mass erase command, a specific
code sequence must be executed to initiate this operation:
1.
Set Bit 3 in FEE0MOD.
2.
Write 0xFFC3 in FEE0ADR.
3.
Write 0x3CFF in FEE0DAT.
4.
Run the mass erase command (Code 0x06) in FEE0CON.
This sequence is illustrated in the following example:
FEE0MOD = 0x08;
FEE0ADR = 0xFFC3;
FEE0DAT = 0x3CFF;
FEE0CON = 0x06;
//Mass erase
command
while (FEE0STA & 0x04){} //Wait for
command to finish
FEE0STA Register
Name:
FEE0STA
Address:
0xFFFF0E00
Default Value:
0x20
Access:
Read only
Function:
This 8-bit, read only register can be read by
user code and reflects the current status of the
Flash/EE memory controller.
Table 14. FEE0STA MMR Bit Designation
Bit
Description
7 to 4
Not used. These bits are not used and always read as 0.
3
Flash/EE interrupt status bit.
Set automatically when an interrupt occurs, that is,
when a command is complete and the Flash/EE
interrupt enable bit in the FEE0MOD register is set.
Cleared automatically when the FEE0STA register is
read by user code.
2
Flash/EE controller busy.
Set automatically when the Flash/EE controller is busy.
Cleared automatically when the controller is not busy.
1
Command fail.
Set automatically when a command written to
FEE0CON fails.
Cleared automatically when the FEE0STA register is
read by user code.
0
Command successful.
Set automatically by MCU when a command is
completed successfully.
Cleared automatically when the FEE0STA register is
read by user code.
FEE0MOD Register
Name:
FEE0MOD
Address:
0xFFFF0E04
Default Value:
0x00
Access:
Read/write access
Function:
This register is written by user code to
configure the mode of operation of the
Flash/EE memory controller.
Table 15. FEE0MOD MMR Bit Designation
Bit
Description
7
Not used. These bits are reserved for future functionality
and should be written as 0 by user code.
6 to 5
Flash/EE security lock bits. These bits must be written as
[6:5] = 10 to complete the Flash/EE security protect
sequence.
4
Flash/EE controller command complete interrupt enable.
Set to 1 by user code to enable the Flash/EE controller
to generate an interrupt upon completion of a Flash/EE
command.
Cleared to disable the generation of a Flash/EE
interrupt upon completion of a Flash/EE command.
3
Flash/EE erase/write enable.
Set by user code to enable the Flash/EE erase and write
access via FEE0CON.
Cleared by user code to disable the Flash/EE erase and
write access via FEE0CON.
2
Reserved.
1
Flash/EE controller abort enable.
Set to 1 by user code to enable the Flash/EE controller
abort functionality.
Cleared by user code to disable the Flash/EE controller
abort functionality.
0
Reserved.
FEE0ADR Registers
Name:
FEE0ADR
Address:
0xFFFF0E10
Default Value:
Nonzero, see the
Access:
Read/write access
Function:
This 16-bit register dictates the address acted
upon when a Flash/EE command is executed
via FEE0CON.
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