参数资料
型号: ADUC7036CCPZ-RL
厂商: Analog Devices Inc
文件页数: 20/132页
文件大小: 0K
描述: IC MCU 96K FLASH DUAL 48LFCSP
标准包装: 2,500
系列: MicroConverter® ADuC7xxx
核心处理器: ARM7
芯体尺寸: 16/32-位
速度: 20.48MHz
连通性: LIN,SPI,UART/USART
外围设备: PSM,温度传感器,WDT
输入/输出数: 9
程序存储器容量: 96KB(48K x 16)
程序存储器类型: 闪存
RAM 容量: 1.5K x 32
电压 - 电源 (Vcc/Vdd): 3.5 V ~ 18 V
数据转换器: A/D 2x16b
振荡器型: 内部
工作温度: -40°C ~ 115°C
封装/外壳: 48-VFQFN 裸露焊盘,CSP
包装: 带卷 (TR)
ADuC7036
Rev. C | Page 116 of 132
LIN (LOCAL INTERCONNECT NETWORK) INTERFACE
The ADuC7036 features high voltage physical interfaces between
the ARM7 MCU core and an external LIN bus. The LIN inter-
face operates as a slave only interface, operating from 1 kBaud
to 20 kBaud, and it is compatible with the LIN 2.0 standard.
The pull-up resistor required for a slave node is on chip,
reducing the need for external circuitry. The LIN protocol is
emulated using the on-chip UART, an IRQ, a dedicated LIN
timer, and the high voltage transceiver (also incorporated on
chip) as shown in Figure 46. The LIN is clocked from the low
power oscillator for the break timer, and a 5 MHz output from
the PLL is used for the synchronous byte timing.
LIN MMR DESCRIPTION
The LIN hardware synchronization (LHS) functionality is con-
trolled through five MMRs. The function of each MMR is as
follows:
LHSSTA: LHS status register. This MMR contains infor-
mation flags that describe the current status on the
interface.
LHSCON0: LHS Control Register 0. This MMR controls
the configuration of the LHS timer.
LHSCON1: LHS start and stop edge control register. This
MMR dictates on which edge of the LIN synchronization
byte the LHS starts/stops counting.
LHSVAL0: LHS synchronization 16-bit timer. This MMR is
controlled by LHSCON0.
LHSVAL1: LHS break timer register.
GPIO_12
FUNCTION
SELECT
GP2CON[20]
GPIO_12
GP2DAT[29]
AND
GPSDAT[21]
UART
LHS
HARDWARE
RxD
TxD
BPF
INTERNAL
SHORT-CIRCUIT
TRIP REFERENCE
INTERNAL
SHORT-CIRCUIT
SENSE
RESISTOR
SHORT-CIRCUIT
CONTROL
HVCFG1[2]
OUTPUT
DISABLE
LIN MODE
HVCFG0[1:0]
INPUT
VOLTAGE
THRESHOLD
REFERENCE
LIN ENABLE
(INTERNAL
PULL-UP)
HVCFG0[5]
FOUR LIN
INTERRUPT
SOURCES:
BREAK LHSSTA[0]
START LHSSTA[1]
STOP LHSSTA[2]
BREAK
ERROR LHSSTA[4]
VDD
RxD ENABLE
LHSCON0[8]
LHSVAL0
LHSVAL1
LHS INTERRUPT
IRQEN[7]
5MHz
131kHz
LHS
INTERRUPT
LOGIC
VDD
SCR
IO_VSS
OVERVOLTAGE
PROTECTION
EXTERNAL
LIN PIN
MASTER ECU
PROTECTION
DIODE
MASTER ECU
PULL-UP
CLOAD
074
74
-0
43
Figure 46. LIN I/O Block Diagram
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