参数资料
型号: ADUM1401CRWZ-RL
厂商: Analog Devices Inc
文件页数: 5/32页
文件大小: 0K
描述: IC DGITAL ISOLATOR 4CH 16-SOIC
设计资源: 16-Bit Fully Isolated Voltage Output Module Using AD5662, ADuM1401, and External Amplifiers (CN0063)
16-Bit Fully Isolated 4 mA to 20 mA Output Module Using AD5662, ADuM1401, and External Amplifiers (CN0064)
16-Bit Fully Isolated Output Module Using AD5422 and ADuM1401 (CN0065)
其它图纸: ADUMx4 Series Quad Block Diagram
标准包装: 1
系列: iCoupler®
输入 - 1 侧/2 侧: 3/1
通道数: 4
电源电压: 2.7 V ~ 5.5 V
电压 - 隔离: 2500Vrms
数据速率: 90Mbps
传输延迟: 32ns
输出类型: 逻辑
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC W
包装: 标准包装
工作温度: -40°C ~ 105°C
产品目录页面: 2766 (CN2011-ZH PDF)
其它名称: ADUM1401CRWZ-RLDKR
Data Sheet
ADuM1400/ADuM1401/ADuM1402
Parameter
Pulse Width Distortion, |t PLH ? t PHL | 5
Change vs. Temperature
Propagation Delay Skew 6
Channel-to-Channel Matching 7
Symbol
PWD
t PSK
t PSKCD /t PSKOD
Min
Typ
11
Max Unit
40
ns
ps/°C
50
ns
50
ns
Test Conditions
C L = 15 pF, CMOS signal levels
C L = 15 pF, CMOS signal levels
C L = 15 pF, CMOS signal levels
C L = 15 pF, CMOS signal levels
ADuM140x BRW
Minimum Pulse Width 3
Maximum Data Rate 4
PW
10
100
ns
Mbps
C L = 15 pF, CMOS signal levels
C L = 15 pF, CMOS signal levels
Propagation Delay 5
Pulse Width Distortion, |t PLH ? t PHL | 5
t PHL , t PLH
PWD
20
32
50
3
ns
ns
C L = 15 pF, CMOS signal levels
C L = 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/°C
C L = 15 pF, CMOS signal levels
Propagation Delay Skew 6
Channel-to-Channel Matching, Codirectional
t PSK
t PSKCD
15
3
ns
ns
C L = 15 pF, CMOS signal levels
C L = 15 pF, CMOS signal levels
Channels 7
Channel-to-Channel Matching, Opposing-
t PSKOD
6
ns
C L = 15 pF, CMOS signal levels
Directional Channels 7
ADuM140x CRW
Minimum Pulse Width 3
Maximum Data Rate 4
PW
90
8.3
120
11.1 ns
Mbps
C L = 15 pF, CMOS signal levels
C L = 15 pF, CMOS signal levels
Propagation Delay 5
Pulse Width Distortion, |t PLH ? t PHL | 5
t PHL , t PLH
PWD
18
27
0.5
32
2
ns
ns
C L = 15 pF, CMOS signal levels
C L = 15 pF, CMOS signal levels
Change vs. Temperature
3
ps/°C
C L = 15 pF, CMOS signal levels
Propagation Delay Skew 6
Channel-to-Channel Matching, Codirectional
t PSK
t PSKCD
10
2
ns
ns
C L = 15 pF, CMOS signal levels
C L = 15 pF, CMOS signal levels
Channels 7
Channel-to-Channel Matching, Opposing-
t PSKOD
5
ns
C L = 15 pF, CMOS signal levels
Directional Channels 7
For All Models
Output Disable Propagation Delay (High/Low
to High Impedance)
Output Enable Propagation Delay (High
Impedance to High/Low)
Output Rise/Fall Time (10% to 90%)
t PHZ , t PLH
t PZH , t PZL
t R /t F
6
6
2.5
8
8
ns
ns
ns
C L = 15 pF, CMOS signal levels
C L = 15 pF, CMOS signal levels
C L = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic
High Output 8
Common-Mode Transient Immunity at Logic
Low Output 8
Refresh Rate
Input Dynamic Supply Current per Channel 9
Output Dynamic Supply Current per Channel 9
|CM H |
|CM L |
f r
I DDI (D)
I DDO (D)
25
25
35
35
1.2
0.19
0.05
kV/μs
kV/μs
Mbps
mA/Mbps
mA/Mbps
V Ix = V DD1 or V DD2 , V CM = 1000 V,
transient magnitude = 800 V
V Ix = 0 V, V CM = 1000 V,
transient magnitude = 800 V
1
2
3
4
5
6
7
8
9
All voltages are relative to their respective ground.
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total V DD1 and V DD2 supply currents as a function of data rate for ADuM1400 / ADuM1401 / ADuM1402 channel configurations.
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
t PHL propagation delay is measured from the 50% level of the falling edge of the V Ix signal to the 50% level of the falling edge of the V Ox signal. t PLH propagation delay is
measured from the 50% level of the rising edge of the V Ix signal to the 50% level of the rising edge of the V Ox signal.
t PSK is the magnitude of the worst-case difference in t PHL or t PLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
CM H is the maximum common-mode voltage slew rate that can be sustained while maintaining V O > 0.8 V DD2 . CM L is the maximum common-mode voltage slew rate
that can be sustained while maintaining V O < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. I | Page 5 of 32
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