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| 型号： | ADUM3223ARZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/20页 |
| 文件大小： | 0K |
| 描述： | IC 3KV ISO HALF BR DRVR 16SOIC |
| 标准包装： | 48 |
| 系列： | iCoupler® |
| 输入 - 1 侧/2 侧： | 2/0 |
| 通道数： | 2 |
| 电源电压： | 3 V ~ 5.5 V，4.5 V ~ 18 V |
| 电压 - 隔离： | 3000Vrms |
| 数据速率： | 1MHz |
| 传输延迟： | 46ns |
| 输出类型： | 逻辑 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC N |
| 包装： | 管件 |
| 工作温度： | -40°C ~ 125°C |
ADuM3223/ADuM4223
The following equation defines the Q factor of the RLC circuit,
which indicates how the ADuM3223 / ADuM4223 output responds
to a step change. For a well-damped output, Q is less than 1.
Adding a series gate resistance dampens the output response.
Data Sheet
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is, therefore, either set or reset by
Q ?
( R SW
1
? R GATE )
?
L TRACE
C GS
the pulses, indicating input logic transitions. In the absence of
logic transitions of more than 1 μs at the input, a periodic set of
refresh pulses indicative of the correct input state are sent to
In Figure 5, the ADuM3223 / ADuM4223 output waveforms
for a 12 V output are shown for a C GS of 2 nF. Note the small
amount of ringing of the output in Figure 5 with C GS of 2 nF,
R SW of 1.1 Ω, R GATE of 0 Ω, and a calculated Q factor of 0.75,
where less than 1 is desired for good damping.
Output ringing can be reduced by adding a series gate resistance
to dampen the response. For applications of less than 1 nF load,
it is recommended to add a series gate resistor of about 2 Ω to 5 Ω.
BOOT-STRAPPED HALF-BRIDGE OPERATION
The ADuM3223 / ADuM4223 are well suited to the operation of
two output gate signals that are referenced to separate grounds,
as in the case of a half-bridge configuration. Because isolated
auxiliary supplies are often expensive, it is beneficial to reduce
the amount of supplies. One method to perform this is to use a
boot-strap configuration for the high-side supply of the
ADuM3223 / ADuM4223 . In this topology, the decoupling
capacitor, C A , acts as the energy storage for the high-side supply,
and is filled whenever the low-side switch is closed, bringing
GND A to GND B . During the charging time of C A , the dv/dt of
the V DDA voltage must be controlled to reduce the possibility of
glitches on the output. Keeping the dv/dt below 10 V/μs is
recommended for the ADuM3223 / ADuM4223 . This can be
controlled by introducing a series resistance, R BOOT , into the
charging path of C A . As an example, if V AUX is 12 V, C A has a
total capacitance of 10 μF, and the forward voltage drop of the
bootstrap diode is 1 V:
ensure dc correctness at the output.
If the decoder receives no internal pulses for more than about
3 μs, the input side is assumed to be unpowered or nonfunc-
tional, in which case, the isolator output is forced to a default
low state by the watchdog timer circuit. In addition, the outputs
are in a low default state while the power is coming up before
the UVLO threshold is crossed.
The ADuM3223 / ADuM4223 is immune to external magnetic
fields. The limitation on the ADuM3223 / ADuM4223 magnetic
field immunity is set by the condition in which induced voltage
in the transformer receiving coil is sufficiently large to either
falsely set or reset the decoder. The following analysis defines
the conditions under which this can occur. The 3 V operating
condition of the ADuM3223 / ADuM4223 is examined because
it represents the most susceptible mode of operation. The pulses
at the transformer output have an amplitude greater than 1.0 V.
The decoder has a sensing threshold at about 0.5 V, therefore
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
V = ( ?dβ / dt ) ∑π r n 2 , n = 1, 2, ... , N
where:
β is the magnetic flux density (gauss).
N is the number of turns in the receiving coil.
r n is the radius of the nth turn in the receiving coil (cm).
R BOOT ?
V AUX ? V D BOOT
C A ? dv dt max
?
12 V ? 1 V
10 μF ? 10 V/μ s
? 0 . 11 Ω
V IA
V IB
1
2
ADuM3223/
ADuM4223
ENCODE
DECODE
16
15
V DDA
V OA
R BOOT
R EXT_A
V D BOOT
D BOOT
V BUS
V PRIM
V PRIM
C DD1
V DD1
GND 1
3
14
C A
GND A
NC
4
13
1
DISABLE
5
12
NC
V PRIM
NC
NC
V DD1
6
7
8
ENCODE
DECODE
11
10
9
V DDB
V OB
C B
GND B
V AUX
R EXT_B
2
NC = NO CONNECT
Figure 22. Circuit of Bootstrapped Half-Bridge Operation
Rev. D | Page 16 of 20
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