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| 型号： | ADUM3223ARZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 3/20页 |
| 文件大小： | 0K |
| 描述： | IC 3KV ISO HALF BR DRVR 16SOIC |
| 标准包装： | 48 |
| 系列： | iCoupler® |
| 输入 - 1 侧/2 侧： | 2/0 |
| 通道数： | 2 |
| 电源电压： | 3 V ~ 5.5 V，4.5 V ~ 18 V |
| 电压 - 隔离： | 3000Vrms |
| 数据速率： | 1MHz |
| 传输延迟： | 46ns |
| 输出类型： | 逻辑 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC N |
| 包装： | 管件 |
| 工作温度： | -40°C ~ 125°C |
Data Sheet
ADuM3223/ADuM4223
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ V DD1 ≤ 5.5 V, 4.5 V ≤ V DD2 ≤ 18 V, unless stated otherwise. All minimum/
maximum specifications apply over T J = ?40°C to 125°C. All typical specifications are at T J = 25°C, V DD1 = 5 V, V DD2 = 12 V. Switching
specifications are tested with CMOS signal levels.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current, Quiescent
Output Supply Current, Per Channel, Quiescent
I DDI(Q)
I DDO(Q)
1.4
2.3
2.4
3.2
mA
mA
Supply Current at 1 MHz
V DD1 Supply Current
V DDA /V DDB Supply Current
I DD1(Q)
I DDA /I DDB(Q)
1.6
5.6
2.5
8.0
mA
mA
Up to 1 MHz, no load
Up to 1 MHz, no load
Input Currents
I IA , I IB
?1
+0.01
+1
μA
0 ≤ V IA , V IB ≤ V DD1
Logic High Input Threshold
Logic Low Input Threshold
V IH
V IL
0.7 × V DD1
0.3 × V DD1
V
V
Logic High Output Voltages
V OAH , V OBH
V DD2 – 0.1
V DD2
V
I Ox = ?20 mA, V Ix = V IxH
Logic Low Output Voltages
V OAL , V OBL
0.0
0.15
V
I Ox = +20 mA, V Ix = V IxL
Undervoltage Lockout, V DD2 Supply
Positive Going Threshold
V DD2UV+
4.1
4.4
V
A-grade
Negative Going Threshold
Hysteresis
V DD2UV?
V DD2UVH
3.2
3.6
0.5
V
V
A-grade
A-grade
Positive Going Threshold
V DD2UV+
6.9
7.4
V
B-grade
Negative Going Threshold
Hysteresis
V DD2UV?
V DD2UVH
5.7
6.2
0.7
V
V
B-grade
B-grade
Positive Going Threshold
V DD2UV+
10.5
11.1
V
C-grade
Negative Going Threshold
Hysteresis
Output Short-Circuit Pulsed Current 1
V DD2UV?
V DD2UVH
I OA(SC) , I OB(SC)
8.9
2.0
9.6
0.9
4.0
V
V
A
C-grade
C-grade
V DD2 = 12 V
Output Pulsed Source Resistance
Output Pulsed Sink Resistance
R OA , R OB
R OA , R OB
0.3
0.3
1.1
0.6
3.0
3.0
?
?
V DD2 = 12 V
V DD2 = 12 V
THERMAL SHUTDOWN TEMPERATURES
Junction Temperature Shutdown, Rising Edge
Junction Temperature Shutdown, Falling Edge
T JR
T JF
150
140
°C
°C
SWITCHING SPECIFICATIONS
Pulse Width 2
Maximum Data Rate 3
PW
50
1
ns
MHz
C L = 2 nF, V DD2 = 12 V
C L = 2 nF, V DD2 = 12 V
Propagation Delay 4
ADuM3223A / ADuM4223A
Propagation Delay Skew 5
Channel-to-Channel Matching 6
Output Rise/Fall Time (10% to 90%)
Dynamic Input Supply Current Per Channel
Dynamic Output Supply Current Per Channel
t DHL , t DLH
t DHL , t DLH
t PSK
t PSKCD
t PSKCD
t R /t F
I DDI(D)
I DDO(D)
31
35
6
43
47
1
1
12
0.05
1.65
54
59
12
5
7
18
ns
ns
ns
ns
ns
ns
mA/Mbps
mA/Mbps
C L = 2 nF, V DD2 = 12 V; see Figure 20
C L = 2 nF, V DD2 = 4.5 V; see Figure 20
C L = 2 nF, V DD2 = 12 V; see Figure 20
C L = 2 nF, V DD2 = 12 V; see Figure 20
C L = 2 nF, V DD2 = 4.5 V; see Figure 20
C L = 2 nF, V DD2 = 12 V; see Figure 20
V DD2 = 12 V
V DD2 = 12 V
Refresh Rate
f r
1.2
Mbps
1
2
3
4
5
6
Short-circuit duration less than 1 μs. Average power must conform to the limit shown under the Absolute Maximum Ratings.
The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed.
The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed.
t DLH propagation delay is measured from the time of the input rising logic high threshold, V IH , to the output rising 10% level of the V Ox signal. t DHL propagation delay is
measured from the input falling logic low threshold, V IL , to the output falling 90% threshold of the V Ox signal. See Figure 20 for waveforms of propagation delay
parameters.
t PSK is the magnitude of the worst-case difference in t DLH and/or t DHL that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions. See Figure 20 for waveforms of propagation delay parameters.
Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels.
Rev. D | Page 3 of 20
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