参数资料
| 型号： | ADV7123KSTZ50 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 2/24页 |
| 文件大小： | 0K |
| 描述： | IC DAC VIDEO 3-CH 50MHZ 48LQFP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 1 |
| 位数： | 10 |
| 数据接口： | 并联 |
| 转换器数目： | 3 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 30mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 托盘 |
| 输出数目和类型： | 6 电流，单极 |
| 采样率（每秒）： | 50M |
| 产品目录页面： | 786 (CN2011-ZH PDF) |
ADV7123
Rev. D | Page 10 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
AA
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
CL
O
CK
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
PSA
V
E
R
SET
G0
G1
G2
G3
G4
G5
G6
G7
G8
G9
COMP
VAA
IOB
GND
VREF
IOB
IOG
IOR
BLANK
SYNC
00
21
5-
00
3
48 47 46 45 44 43 42
41 40 39
38 37
35
34
33
30
31
32
36
29
28
27
25
26
2
3
4
7
6
5
1
8
9
10
12
11
13 14 15 16 17 18 19 20 21 22 23 24
PIN 1
INDICATOR
ADV7123
TOP VIEW
(Not to Scale)
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Description
1 to 10,
14 to 23,
39 to 48
G0 to G9,
B0 to B9,
R0 to R9
Red, Green, and Blue Pixel Data Inputs (TTL Compatible). Pixel data is latched on the rising edge of CLOCK. R0,
G0, and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the
regular printed circuit board (PCB) power or ground plane.
11
BLANK
Composite Blank Control Input (TTL Compatible). A Logic 0 on this control input drives the analog outputs,
IOR, IOB, and IOG, to the blanking level. The BLANK signal is latched on the rising edge of CLOCK. While
BLANK is a Logic 0, the R0 to R9, G0 to G9, and B0 to B9 pixel inputs are ignored.
12
SYNC
Composite Sync Control Input (TTL Compatible). A Logic 0 on the SYNC input switches off a 40 IRE current
source. This is internally connected to the IOG analog output. SYNC does not override any other control or
data input; therefore, it should only be asserted during the blanking interval. SYNC is latched on the rising
edge of CLOCK. If sync information is not required on the green channel, the SYNC input should be tied to
Logic 0.
13, 29, 30
VAA
Analog Power Supply (5 V ± 5%). All VAA pins on the ADV7123 must be connected.
24
CLOCK
Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0 to R9, G0 to G9, B0 to B9, SYNC, and
BLANK pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be driven
by a dedicated TTL buffer.
25, 26
GND
Ground. All GND pins must be connected.
27, 31, 33
IOB, IOG, IOR
Differential Red, Green, and Blue Current Outputs (High Impedance Current Sources). These RGB video
outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly terminated 75 Ω load. If
the complementary outputs are not required, these outputs should be tied to ground.
28, 32, 34
IOB, IOG, IOR
Red, Green, and Blue Current Outputs. These high impedance current sources are capable of directly driving a
doubly terminated 75 Ω coaxial cable. All three current outputs should have similar output loads whether or
not they are all being used.
35
COMP
Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1 μF ceramic capacitor
must be connected between COMP and VAA.
36
VREF
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADV7123KSTZ50 | 制造商:Analog Devices 功能描述:IC DAC 10BIT 330MSPS LQFP-48 |
| ADV7123SCP170EP-RL | 功能描述:视频 IC 5V supply only up to 140MHz IC RoHS:否 制造商:Fairchild Semiconductor 工作电源电压:5 V 电源电流:80 mA 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-28 封装:Reel |
| ADV7125 | 制造商:AD 制造商全称:Analog Devices 功能描述:CMOS, 330 MHz Triple 8-Bit High Speed Video DAC |
| ADV7125_11 | 制造商:AD 制造商全称:Analog Devices 功能描述:CMOS, 330 MHz Triple 8-Bit High Speed Video DAC |
| ADV7125BCPZ170 | 功能描述:IC DAC VIDEO 3CH 330MHZ 48VFQFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 标准包装:1 系列:- 设置时间:4.5µs 位数:12 数据接口:串行，SPI? 转换器数目:1 电压电源:单电源 功率耗散（最大）:- 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOICN 包装:剪切带 (CT) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:* 其它名称:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
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