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参数资料
| 型号： | ADV7125WBCPZ170 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 3/16页 |
| 文件大小： | 0K |
| 描述： | IC DAC VIDEO 3-CH 330MHZ 48VFQFN |
| 标准包装： | 1 |
| 位数： | 8 |
| 转换器数目： | 3 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 30mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 托盘 |
| 输出数目和类型： | 6 电流，单极 |
| 采样率（每秒）： | 170M |
ADV7125
Rev. C | Page 11 of 16
CIRCUIT DESCRIPTION AND OPERATION
The ADV7125 contains three 8-bit DACs, with three input
channels, each containing an 8-bit register. Also integrated
on board the part is a reference amplifier. The CRT control
functions, BLANK and SYNC, are integrated on board the
ADV7125.
DIGITAL INPUTS
There are 24 bits of pixel data (color information), R0 to R7,
G0 to G7, and B0 to B7, latched into the device on the rising
edge of each clock cycle. This data is presented to the three 8-bit
DACs and then converted to three analog (RGB) output wave-
forms (see Figure 4).
CLOCK
DATA
DIGITAL INPUTS
(R7 TO R0, G7 TO G0,
B7 TO B0,
SYNC, BLANK)
ANALOG OUTPUTS
(IOR, IOR, IOG, IOG,
IOB, IOB)
03
09
7-
00
4
Figure 4. Video Data Input/Output
The ADV7125 has two additional control signals that are latched
to the analog video outputs in a similar fashion. BLANK and
SYNC are each latched on the rising edge of CLOCK to maintain
synchronization with the pixel data stream.
The BLANK and SYNC functions allow for the encoding of
these video synchronization signals onto the RGB video output.
This is done by adding appropriately weighted current sources
to the analog outputs, as determined by the logic levels on the
BLANK and SYNC digital inputs.
Figure 5 shows the analog output, RGB video waveform of the
ADV7125. The influence of SYNC and BLANK on the analog
video waveform is illustrated.
Table 7 details the resultant effect on the analog outputs of
BLANK and SYNC.
All these digital inputs are specified to accept TTL logic levels.
CLOCK INPUT
The CLOCK input of the ADV7125 is typically the pixel clock
rate of the system. It is also known as the dot rate. The dot rate,
and thus the required CLOCK frequency, is determined by the
on-screen resolution, according to the following equation:
Dot Rate = (Horiz Res) × (Vert Res) × (Refresh
Rate)/(Retrace Factor)
where:
Horiz Res is the number of pixels per line.
Vert Res is the number of lines per frame.
Refresh Rate is the horizontal scan rate. This is the rate at which
the screen must be refreshed, typically 60 Hz for a noninterlaced
system, or 30 Hz for an interlaced system.
Retrace Factor is the total blank time factor. This takes into
account that the display is blanked for a certain fraction of the
total duration of each frame (for example, 0.8).
Therefore, for a graphics system with a 1024 × 1024 resolution,
a noninterlaced 60 Hz refresh rate, and a retrace factor of 0.8,
Dot Rate = 1024 × 1024 × 60/0.8 = 78.6 MHz
The required CLOCK frequency is thus 78.6 MHz. All video
data and control inputs are latched into the ADV7125 on the
rising edge of CLOCK, as previously described in the Digital
Inputs section. It is recommended that the CLOCK input to the
ADV7125 be driven by a TTL buffer (for example, the 74F244).
RED AND BLUE
NOTES
1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75 LOAD.
2. VREF = 1.235V, RSET = 530.
3. RS-343 LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.
mA
V
18.67
0.7
00
mA
V
26.0
0.975
WHITE LEVEL
BLANK LEVEL
SYNC LEVEL
7.2
0.271
00
GREEN
03
09
7-
0
05
Figure 5. Typical RGB Video Output Waveform
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADV7125WBCPZ170-RL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| ADV7125WBSTZ170 | 制造商:Analog Devices 功能描述:330MHZ TRIPLE 8-BIT HIGH SPEED VIDEO DAC - Rail/Tube |
| ADV7125WBSTZ170-RL | 制造商:AD 制造商全称:Analog Devices 功能描述:CMOS, 330 MHz Triple 8-Bit High Speed Video DAC |
| ADV7127 | 制造商:AD 制造商全称:Analog Devices 功能描述:CMOS, 240 MHz 10-Bit High Speed Video DAC |
| ADV7127JR240 | 制造商:Rochester Electronics LLC 功能描述:SINGLE HIGH SPEED VIDEO DAC I.C. - Bulk 制造商:Analog Devices 功能描述: |
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