参数资料
型号: ADV7127JRUZ240
厂商: Analog Devices Inc
文件页数: 3/16页
文件大小: 0K
描述: IC DAC VIDEO240MHZ 3.3/5 24TSSOP
产品培训模块: Data Converter Fundamentals
DAC Architectures
标准包装: 1
设置时间: 15ns
位数: 10
数据接口: 并联
转换器数目: 1
电压电源: 单电源
功率耗散(最大): 30mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 24-TSSOP
包装: 管件
输出数目和类型: 2 电流,单极
采样率(每秒): 240M
产品目录页面: 786 (CN2011-ZH PDF)
ADV7127
–11–
REV. 0
3 V–Typical Performance Characteristics
(VAA = +3 V, VREF = 1.235 V, IOUT =17.62
A, 50
Doubly Terminated Load, Differential Output Loading, TA = +25 C)
FREQUENCY – MHz
70
0
0.1
2.51
5.04
20.2
40.4
100
60
50
40
20
10
30
SFDR (SE)
SFDR (DE)
SFDR
dBc
Figure 11. SFDR vs. fOUT @ fCLOCK =
140 MHz (Single-Ended and
Differential)
FREQUENCY – MHz
76
74
56
0
160
50
100
140
68
62
60
58
72
70
64
66
4th HARMONIC
3rd HARMONIC
2nd HARMONIC
THD
dBc
Figure 14. THD vs. fCLOCK @ fOUT =
2 MHz (2nd, 3rd and 4th Harmonics)
VAA = 3.3V
1
–5.0
–45.0
–85.0
0kHz
START
35.0MHz
70.0MHz
STOP
SFDR
dBm
CLK = 140MHz
fOUT = 2.5MHz
SING O/P
2
Figure 17. Single-Tone SFDR @
fCLOCK = 140 MHz (fOUT1 = 2 MHz)
FREQUENCY – MHz
80
0
70
40
30
20
10
60
50
0.1
100
1.0
2.51
5.04
20.2
40.4
SFDR (SE)
SFDR (DE)
SFDR
dBc
Figure 12. SFDR vs. fOUT @ fCLOCK =
50 MHz (Single-Ended and
Differential)
IOUT – mA
1.0
0.9
0.0
020
2
17.62
0.4
0.3
0.2
0.1
0.6
0.5
0.8
0.7
LINEARITY
LSBs
Figure 15. Linearity vs. IOUT
VAA = 3.3V
1
–5.0
–45.0
–85.0
0kHz
START
35.0MHz
70.0MHz
STOP
SFDR
dBm
CLK = 140MHz
fOUT = 20MHz
SING O/P
2
Figure 18. Single-Tone SFDR @
fCLOCK = 140 MHz (fOUT1 = 20 MHz)
TEMPERATURE – C
72.0
71.8
70.4
0
165
20
85
145
71.2
71.0
70.8
70.6
71.6
71.4
SFDR (fOUT = 1MHz)
SFDR
dBc
Figure 13. SFDR vs. Temperature @
fCLOCK = 50 MHz, (fOUT = 1 MHz)
1.00
0.50
0.00
–0.50
0.75
1023
–0.42
ERROR
LSB
–1.00
CODE– INL
Figure 16. Typical Linearity
VAA = 3.3V
1
–5.0
–45.0
–85.0
0kHz
START
35.0MHz
70.0MHz
STOP
SFDR
dBm
CLK = 140MHz
DUAL TONE
SING O/P
2
Figure 19. Dual-Tone SFDR @ fCLOCK
= 140 MHz (fOUT1 = 13.5 MHz, fOUT2 =
14.5 MHz)
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