参数资料
型号: ADV7189BBSTZ
厂商: Analog Devices Inc
文件页数: 46/104页
文件大小: 0K
描述: IC VIDEO DECODER SDTV 80-LQFP
标准包装: 1
类型: 视频解码器
应用: 机顶盒,视频播放器,录音机
电压 - 电源,模拟: 3.15 V ~ 3.45 V
电压 - 电源,数字: 1.65 V ~ 2 V
安装类型: 表面贴装
封装/外壳: 80-LQFP
供应商设备封装: 80-LQFP(14x14)
包装: 托盘
ADV7189B
Rev. B | Page 46 of 104
04983-
0-
027
FIELD 1
622
623
624
625
12
3
4
5
6
7
8
9
10
11
23
24
310
311
312
313
314
315
316
317
318
319
320
321
322
323
336
337
PVBEG[4:0] = 0x1
PVEND[4:0] = 0x4
PFTOG[4:0] = 0x6
FIELD 2
OUTPUT
VIDEO
FIELD
OUTPUT
HS
OUTPUT
VS
OUTPUT
VIDEO
FIELD
OUTPUT
HS
OUTPUT
VS
OUTPUT
PVBEG[4:0] = 0x1
PVEND[4:0] = 0x4
PFTOG[4:0] = 0x6
Figure 27. PAL Typical Vsync/Field Positions Using Register Writes in
216H
Table 57
04983-0-028
ADVANCE BEGIN OF
VSYNC BY PVBEG[4:0]
DELAY BEGIN OF
VSYNC BY PVBEG[4:0]
VSYNC BEGIN
PVBEGSIGN
ODD FIELD?
0
1
NO
YES
PVBEGDELO
VSBHO
ADDITIONAL
DELAY BY
1 LINE
ADVANCE BY
0.5 LINE
1
0
1
0
PVBEGDELE
VSBHE
ADDITIONAL
DELAY BY
1 LINE
ADVANCE BY
0.5 LINE
1
0
1
0
NOT VALID FOR USER
PROGRAMMING
Figure 28. PAL Vsync Begin
PVBEGDELO PAL Vsync Begin Delay on Odd Field,
Address 0xE8[7]
When PVBEGDELO is 0 (default), there is no delay.
Setting PVBEGDELO to 1 delays Vsync going high on an odd
field by a line relative to PVBEG.
PVBEGDELE PAL Vsync Begin Delay on Even Field,
Address 0xE8[6]
When PVBEGDELE is 0, there is no delay.
Setting PVBEGDELE to 1 (default) delays Vsync going high on
an even field by a line relative to PVBEG.
PVBEGSIGN PAL Vsync Begin Sign, Address 0xE8[5]
Setting PVBEGSIGN to 0 delays the beginning of Vsync. Set for
user manual programming.
Setting PVBEGSIGN to 1 (default) advances the beginning of
Vsync. Not recommended for user programming.
PVBEG[4:0] PAL Vsync Begin, Address 0xE8[4:0]
The default value of PVBEG is 00101, indicating the PAL Vsync
begin position.
For all NTSC/PAL Vsync timing controls, both the V bit in the
AV code and the Vsync on the VS pin are modified.
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