参数资料
型号: ADV7321KSTZ
厂商: Analog Devices Inc
文件页数: 39/88页
文件大小: 0K
描述: IC VID ENC 6-12BIT DAC'S 64LQFP
标准包装: 1
类型: 视频编码器
应用: EVD,DVD,SD/PS/HDTV
电压 - 电源,模拟: 2.5V
电压 - 电源,数字: 2.5V
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 托盘
ADV7320/ADV7321
Rev. A | Page 44 of 88
NO FSC RESET APPLIED
FSC PHASE = FIELD 4 OR 8
307
310
313
320
DISPLAY
START OF FIELD 4 OR 8
FSC RESET APPLIED
FSC RESET PULSE
FSC PHASE = FIELD 1
307
310
313
320
DISPLAY
START OF FIELD 4 OR 8
05067-037
Figure 61. Subcarrier Reset Timing Diagram
LCC1
GLL
P19–P10
ADV7183A
VIDEO
DECODER
COMPOSITE
VIDEO1
CLKIN_A
RTC_SCR_TR
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
Y9–Y0/S9–S05
RTC
LOW
H/L TRANSITION
COUNT START
128
TIME SLOT 01
13
0
14 BITS
SUBCARRIER
PHASE
14
21
19
FSC PLL INCREMENT2
VALID
SAMPLE
INVALID
SAMPLE
6768
4 BITS
RESERVED
0
SEQUENCE
BIT3
RESET
BIT4
RESERVED
ADV7320/
ADV7321
NOTES
1FOR EXAMPLE, VCR OR CABLE.
2FSC PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7320/ADV7321 FSC DDS REGISTER IS FSC. PLL INCREMENTS BITS 21:0
AND BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS
OF THE ADV7320/ADV7321.
3SEQUENCE BIT PAL: 0 = LINE NORMAL, 1 = LINE INVERTED; NTSC: 0 = NO CHANGE.
4RESET ADV7320/ADV7321 DDS.
5SELECTED BY REGISTER ADDRESS 0x01, BIT 7.
05067-038
8/LINE-
LOCKED
CLOCK
5 BITS
RESERVED
Figure 62. RTC Timing and Connections
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