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| 型号： | ADZS-21469-EZBRD |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/62页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL EZ BOARD ADSP-21469 |
| 特色产品： | SHARC? 21469 EZ-KIT? and EZ-Board? for SHARC Processors |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | DSP |
| 适用于相关产品： | ADSP-2146x |
| 所含物品： | 板 |
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Preliminary Technical Data
? Supporting data formats from 7 to 12 bits per frame.
ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469
second updating of the PWM registers is implemented at the
? Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
In conjunction with the general-purpose timer functions, auto-
baud detection is supported.
Timers
The ADSP-2146x has a total of three timers: a core timer that
can generate periodic software interrupts and two general pur-
pose timers that can generate periodic interrupts and be
independently set to operate in one of three modes:
? Pulse waveform generation mode
? Pulse width count/capture mode
? External event watchdog mode
The core timer can be configured to use FLAG3 as a timer
expired signal, and each general-purpose timer has one bidirec-
tional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register,
a 32-bit period register, and a 32-bit pulse width register. A sin-
gle control and status register enables or disables both general-
purpose timers independently.
2-Wire Interface Port (TWI)
The TWI is a bidirectional 2-wire, serial bus used to move 8-bit
data while maintaining compliance with the I 2 C bus protocol.
The TWI master incorporates the following features:
? 7-bit addressing
? Simultaneous master and slave operation on multiple
device systems with support for multi master data
arbitration
? Digital filtering and timed event processing
? 100 kbps and 400 kbps data rates
? Low interrupt rate
Pulse-Width Modulation
The PWM module is a flexible, programmable, PWM waveform
generator that can be programmed to generate the required
switching patterns for various applications related to motor and
engine control or audio power control. The PWM generator can
generate either center-aligned or edge-aligned PWM wave-
forms. In addition, it can generate complementary signals on
two outputs in paired mode or independent signals in non-
paired mode (applicable to a single group of four PWM
waveforms).
The entire PWM module has four groups of four PWM outputs
each. Therefore, this module generates 16 PWM outputs in
total. Each PWM group produces two pairs of PWM signals on
the four PWM outputs.
The PWM generator is capable of operating in two distinct
modes while generating center-aligned PWM waveforms: single
update mode or double update mode. In single update mode the
duty cycle values are programmable only once per PWM period.
This results in PWM patterns that are symmetrical about the
mid-point of the PWM period. In double update mode, a
mid-point of the PWM period. In this mode, it is possible to
produce asymmetrical PWM patterns that produce lower har-
monic distortion in three-phase PWM inverters.
Link Ports
Two 8-bit wide link ports can connect to the link ports of other
DSPs or peripherals. Link ports are bidirectional ports having
eight data lines, an acknowledge line and a clock line. Link ports
can operate at a maximum frequency of 166 MHz.
MediaLB
The ADSP-21462W, ADSP-21465W and ADSP-21469W have
an MLB interface which allows the processor to function as a
media local bus device. It includes support for both 3-pin as well
as 5-pin media local bus protocols. It supports speeds up to 1024
FS (49.25 Mbits/sec, FS = 48.1 kHz) and up to 31 logical chan-
nels, with up to 124 bytes of data per media local bus frame.
ROM Based Security
The ADSP-2146x has a ROM security feature that provides
hardware support for securing user software code by preventing
unauthorized reading from the internal code when enabled.
When using this feature, the processor does not boot-load any
external code, executing exclusively from internal SRAM/ROM.
Additionally, the processor is not freely accessible via the JTAG
port. Instead, a unique 64-bit key, which must be scanned in
through the JTAG or Test Access Port will be assigned to each
customer. The device will ignore a wrong key. Emulation fea-
tures and external boot modes are only available after the
correct key is scanned.
SYSTEM DESIGN
The following sections provide an introduction to system design
options and power supply issues.
Program Booting
The internal memory of the ADSP-2146x boots at system
power-up from an 8-bit EPROM via the external port, link port,
an SPI master, or an SPI slave. Booting is determined by the
The “Running Reset” feature allows a user to perform a reset of
the processor core and peripherals, but without resetting the
PLL and DDR2 DRAM controller, or performing a Boot. The
functionality of the CLKOUT/RESETOUT/RUNRSTIN pin has
now been extended to also act as the input for initiating a Run-
ning Reset. For more information, see the ADSP-2146x SHARC
Processor Hardware Reference .
Power Supplies
The processors have separate power supply connections for the
internal (V DD_INT ), external (V DD_EXT ), and analog
(V DD_A /V SS_A ) power supplies. The internal and analog supplies
must meet the V DD_INT specifications. The external supply must
meet the V DD_EXT specification. All external supply pins must
be connected to the same power supply.
Rev. PrC
| Page 11 of 62 | January 2009
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