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参数资料
型号： AGLE600V2-FFGG484C
元件分类： FPGA
英文描述： FPGA, 13824 CLBS, 600000 GATES, PBGA256
封装： 17 X 17 MM, 1.60 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, FBGA-256
文件页数： 153/156页
文件大小： 5023K
代理商： AGLE600V2-FFGG484C
IGLOOe DC and Switching Characteristics
2- 82
Advance v0.3
Timing Characteristics
1.5 V DC Core Voltage
1.2 V DC Core Voltage
Table 2-125 Output DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
Std.
Units
tDDROCLKQ
Clock-to-Out of DDR for Output DDR
1.07
ns
tDDROSUD1
Data_F Data Setup for Output DDR
0.67
ns
tDDROSUD2
Data_R Data Setup for Output DDR
0.67
ns
tDDROHD1
Data_F Data Hold for Output DDR
0.00
ns
tDDROHD2
Data_R Data Hold for Output DDR
0.00
ns
tDDROCLR2Q
Asynchronous Clear-to-Out for Output DDR
1.38
ns
tDDROREMCLR
Asynchronous Clear Removal Time for Output DDR
0.00
ns
tDDRORECCLR
Asynchronous Clear Recovery Time for Output DDR
0.23
ns
tDDROWCLR1
Asynchronous Clear Minimum Pulse Width for Output DDR
0.19
ns
tDDROCKMPWH
Clock Minimum Pulse Width HIGH for the Output DDR
0.31
ns
tDDROCKMPWL
Clock Minimum Pulse Width LOW for the Output DDR
0.28
ns
FDDOMAX
Maximum Frequency for the Output DDR
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-126 Output DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC =1.14V
Parameter
Description
Std.
Units
tDDROCLKQ
Clock-to-Out of DDR for Output DDR
1.60
ns
tDDROSUD1
Data_F Data Setup for Output DDR
1.09
ns
tDDROSUD2
Data_R Data Setup for Output DDR
1.16
ns
tDDROHD1
Data_F Data Hold for Output DDR
0.00
ns
tDDROHD2
Data_R Data Hold for Output DDR
0.00
ns
tDDROCLR2Q
Asynchronous Clear-to-Out for Output DDR
1.99
ns
tDDROREMCLR
Asynchronous Clear Removal Time for Output DDR
0.00
ns
tDDRORECCLR
Asynchronous Clear Recovery Time for Output DDR
0.24
ns
tDDROWCLR1
Asynchronous Clear Minimum Pulse Width for Output DDR
0.19
ns
tDDROCKMPWH
Clock Minimum Pulse Width HIGH for the Output DDR
0.31
ns
tDDROCKMPWL
Clock Minimum Pulse Width LOW for the Output DDR
0.28
ns
FDDOMAX
Maximum Frequency for the Output DDR
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
相关PDF资料
PDF描述
AGLE600V2-FG256C FPGA, 13824 CLBS, 600000 GATES, PBGA256
AGLE600V2-FGG256C FPGA, 13824 CLBS, 600000 GATES, PBGA256
AGLE600V2-FGG484C FPGA, 13824 CLBS, 600000 GATES, PBGA256
AGLE600V5-FFG256C FPGA, 13824 CLBS, 600000 GATES, PBGA256
AGLE600V5-FFG484C FPGA, 13824 CLBS, 600000 GATES, PBGA256
相关代理商/技术参数
参数描述
AGLE600V2-FFGG896 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE600V2-FFGG896ES 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE600V2-FFGG896I 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE600V2-FFGG896PP 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE600V2-FG256 功能描述:IC FPGA 1KB FLASH 600K 256-FBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:IGLOOe 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27）
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