收藏本站
参数资料
型号： AGLE600V5-FFG256C
元件分类： FPGA
英文描述： FPGA, 13824 CLBS, 600000 GATES, PBGA256
封装： 17 X 17 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-256
文件页数： 31/156页
文件大小： 5023K
代理商： AGLE600V5-FFG256C
IGLOOe DC and Switching Characteristics
2- 112
Advance v0.3
Advance v0.1
(continued)
Table 2-13 Summary of I/O Output Buffer Power (per pin) – Default I/O
Software Settings1 was updated to change PDC3 to PDC7. The table notes were
updated to reflect that power was measured on VCCI. Table note 4 is new.
2-10
Table 2-15 Different
Components
Contributing
to
the
Static
Power
Consumption in IGLOO Devices and Table 2-17 Different Components
Contributing to the Static Power Consumption in IGLOO Devices were
updated to add PDC6 and PDC7, and to change the definition for PDC5 to bank
quiescent power.
2-11,
2-12
A
table
subtitle
was
added
for
Table 2-17 Different
Components
Contributing to the Static Power Consumption in IGLOO Devices
2-12
The "Total Static Power Consumption—PSTAT" section was updated to revise
the calculation of PSTAT, including PDC6 and PDC7.
2-13
Footnote 1 was updated to include information about PAC13. The PLL
Contribution equation was changed from: PPLL = PAC13 + PAC14 * FCLKOUT to PPLL
= PDC4 + PAC13 * FCLKOUT.
2-14
The "Timing Model" was updated to be consistent with the revised timing
numbers.
2-16
In Table 2-21 Summary of Maximum and Minimum DC Input Levels, TJ was
changed to TA in notes 1 and 2.
2-21
Table 2-31 Schmitt Trigger Input Hysteresis was updated to included a
hysteresis value for 1.2 V LVCMOS (Schmitt trigger mode).
2-28
All AC Loading figures for single-ended I/O standards were changed from
Datapaths at 35 pF to 5 pF.
N/A
The "1.2 V LVCMOS (JESD8-12A)" section is new.
2-41
Advance v0.4
(December 2007)
This document was previously in datasheet Advance v0.4. As a result of
moving to the handbook format, Actel has restarted the version numbers. The
new version number is Advance v0.1.
N/A
Advance v0.3
(September 2007)
Table 2-4 IGLOOe CCC/PLL Specification and Table 2-5 IGLOOe CCC/PLL
Specification were updated.
2-18,
2-19
The "During Flash*Freeze Mode" section was updated to include information
about the output of the I/O to the FPGA core
.
2-60
Figure 2-38 Flash*Freeze Mode Type 1 – Timing Diagram was updated to
modify the LSICC signal.
2-56
Table 2-32 Flash*Freeze Pin Location in IGLOOe Family Packages (device-
independent) was updated for the FG896 package.
2-64
Figure 2-40 Flash*Freeze Mode Type 2 – Timing Diagram was updated to
modify the LSICC Signal.
2-58
Information regarding calculation of the quiescent supply current was added
to the "Quiescent Supply Current" section.
3-6
Table 3-8 Quiescent Supply Current (IDD), IGLOOe Flash*Freeze Mode was
updated.
3-6
Table 3-9 Quiescent Supply Current (IDD), IGLOOe Sleep Mode (VCC = 0 V)
was updated.
3-6
Table 3-11 Quiescent Supply Current, No IGLOOe Flash*Freeze Mode1 was
updated.
3-6
Previous Version
Changes in Current Version (Advance v0.3)
Page
相关PDF资料
PDF描述
AGLE600V5-FFG484C FPGA, 13824 CLBS, 600000 GATES, PBGA256
AGLE600V5-FFGG256C FPGA, 13824 CLBS, 600000 GATES, PBGA256
AGLE600V5-FFGG484C FPGA, 13824 CLBS, 600000 GATES, PBGA484
AGLE600V5-FG256C FPGA, 13824 CLBS, 600000 GATES, PBGA256
AGLE600V5-FG484C FPGA, 13824 CLBS, 600000 GATES, PBGA484
相关代理商/技术参数
参数描述
AGLE600V5-FFG484 制造商:Microsemi Corporation 功能描述:FPGA IGLOOE 600K GATES 130NM 1.5V 484FBGA - Trays
AGLE600V5-FFG896 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE600V5-FFG896ES 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE600V5-FFG896I 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE600V5-FFG896PP 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*