参数资料
型号: AGLP030V2-CS289
厂商: Microsemi SoC
文件页数: 95/134页
文件大小: 0K
描述: IC FPGA IGLOO PLUS 30K 289-CSP
标准包装: 152
系列: IGLOO PLUS
逻辑元件/单元数: 792
输入/输出数: 120
门数: 30000
电源电压: 1.14 V ~ 1.575 V
安装类型: 表面贴装
工作温度: 0°C ~ 70°C
封装/外壳: 289-TFBGA,CSBGA
供应商设备封装: 289-CSP(14x14)
IGLOO PLUS Low Power Flash FPGAs
Revision 16
2-49
Output Enable Register
Timing Characteristics
1.5 V DC Core Voltage
Figure 2-16 Output Enable Register Timing Diagram
50%
Preset
Clear
EOUT
CLK
D_Enable
50%
tOESUDtOEHD
50%
tOECLKQ
1
0
tOERECPRE
tOEREMPRE
tOERECCLR
tOEREMCLR
tOEWCLR
tOEWPRE
tOEPRE2Q
tOECLR2Q
tOECKMPWH tOECKMPWL
50%
Table 2-78 Output Enable Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
Std. Units
tOECLKQ
Clock-to-Q of the Output Enable Register
0.68
ns
tOESUD
Data Setup Time for the Output Enable Register
0.33
ns
tOEHD
Data Hold Time for the Output Enable Register
0.00
ns
tOECLR2Q
Asynchronous Clear-to-Q of the Output Enable Register
0.84
ns
tOEPRE2Q
Asynchronous Preset-to-Q of the Output Enable Register
0.91
ns
tOEREMCLR
Asynchronous Clear Removal Time for the Output Enable Register
0.00
ns
tOERECCLR
Asynchronous Clear Recovery Time for the Output Enable Register
0.24
ns
tOEREMPRE
Asynchronous Preset Removal Time for the Output Enable Register
0.00
ns
tOERECPRE
Asynchronous Preset Recovery Time for the Output Enable Register
0.24
ns
tOEWCLR
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
0.19
ns
tOEWPRE
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
0.19
ns
tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register
0.31
ns
tOECKMPWL
Clock Minimum Pulse Width Low for the Output Enable Register
0.28
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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