参数资料
| 型号： | AGLP030V5-CSG289I |
| 厂商： | Microsemi SoC |
| 文件页数： | 32/134页 |
| 文件大小： | 0K |
| 描述： | IC FPGA IGLOO PLUS 30K 289-CSP |
| 标准包装： | 152 |
| 系列： | IGLOO PLUS |
| 逻辑元件/单元数： | 792 |
| 输入/输出数： | 120 |
| 门数： | 30000 |
| 电源电压： | 1.425 V ~ 1.575 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 289-TFBGA，CSBGA |
| 供应商设备封装： | 289-CSP（14x14） |
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Revision 16
5-1
5 – Datasheet Information
List of Changes
The following table lists critical changes that were made in each revision of the IGLOO PLUS datasheet.
Revision
Changes
Page
Revision 16
(December 2012)
The "IGLOO PLUS Ordering Information" section has been updated to mention "Y"
as "Blank" mentioning "Device Does Not Include License to Implement IP Based on
the Cryptography Research, Inc. (CRI) Patent Portfolio" (SAR 43175).
The note in Table 2-90 IGLOO PLUS CCC/PLL Specification and Table 2-91
IGLOO PLUS CCC/PLL Specification referring the reader to SmartGen was revised
to refer instead to the online help associated with the core (SAR 42566).
Live at Power-Up (LAPU) has been replaced with ’Instant On’.
NA
Revision 15
(October 2012)
Values updated for IGLOO PLUS V2 or V5 Devices, 1.5 V Core Supply Voltage in
IGLOO PLUS Devices and for IGLOO PLUS V2 Devices, 1.2 V Core Supply Voltage
in IGLOO PLUS Devices (SAR 31988). Also added a new Note to the two tables.
Libero Integrated Design Environment (IDE) was changed to Libero System-on-Chip
(SoC) throughout the document (SAR 40277).
N/A
Revision 14
(September 2012)
The "Security" section was modified to clarify that Microsemi does not support read-
back of programmed data.
Revision 13
(June 2012)
Figure 2-30 FIFO Read and Figure 2-31 FIFO Write have been added (SAR
34843).
Updated the terminology used in Timing Characteristics in the following tables:
Table 2-96 FIFO and Table 2-97 FIFO (SAR 38236).
The following sentence was removed from the "VMVx I/O Supply Voltage (quiet)"
section in the "Pin Descriptions and Packaging" section: "Within the package, the
VMV plane is decoupled from the simultaneous switching noise originating from the
output buffer VCCI domain" and replaced with “Within the package, the VMV plane
biases the input stage of the I/Os in the I/O banks” (SAR 38320). The datasheet
mentions that "VMV pins must be connected to the corresponding VCCI pins" for an
ESD enhancement.
Revision 12
(March 2012)
were revised to clarify that although no existing security measures can give an
absolute guarantee, Microsemi FPGAs implement the best security available in the
industry (SAR 34664).
The Y security option and Licensed DPA Logo were added to the "IGLOO PLUS
Ordering Information" section. The trademarked Licensed DPA Logo identifies that a
product is covered by a DPA counter-measures license from Cryptography Research
(SAR 34724).
The "Specifying I/O States During Programming" section is new (SAR 34695).
The following sentence was removed from the "Advanced Architecture" section:
"In addition, extensive on-chip programming circuitry allows for rapid, single-voltage
(3.3 V) programming of IGLOO PLUS devices via an IEEE 1532 JTAG interface"
(SAR 34684).
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相关代理商/技术参数 |
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| AGLP030-V5CSG289PP | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP030-V5FCS289 | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP030V5-FCS289 | 制造商:Microsemi Corporation 功能描述:FPGA IGLOO PLUS FAMILY 30K GATES 256 CELLS 130NM (CMOS) TECH - Trays |
| AGLP030-V5FCS289ES | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP030-V5FCS289I | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
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