参数资料
型号: AGLP125V2-CS289I
厂商: Microsemi SoC
文件页数: 132/134页
文件大小: 0K
描述: IC FPGA IGLOO PLUS 125K 289-CSP
标准包装: 152
系列: IGLOO PLUS
逻辑元件/单元数: 3120
RAM 位总计: 36864
输入/输出数: 212
门数: 125000
电源电压: 1.14 V ~ 1.575 V
安装类型: 表面贴装
工作温度: -40°C ~ 85°C
封装/外壳: 289-TFBGA,CSBGA
供应商设备封装: 289-CSP(14x14)
IGLOO PLUS Low Power Flash FPGAs
Revision 16
3-3
FF
Flash*Freeze Mode Activation Pin
The FF pin is a dedicated input pin used to enter and exit Flash*Freeze mode. The FF pin is active low,
has the same characteristics as a single-ended I/O, and must meet the maximum rise and fall times.
When Flash*Freeze mode is not used in the design, the FF pin is available as a regular I/O.
When Flash*Freeze mode is used, the FF pin must not be left floating to avoid accidentally entering
Flash*Freeze mode. While in Flash*Freeze mode, the Flash*Freeze pin should be constantly asserted.
The Flash*Freeze pin can be used with any single-ended I/O standard supported by the I/O bank in
which the pin is located, and input signal levels compatible with the I/O standard selected. The FF pin
should be treated as a sensitive asynchronous signal. When defining pin placement and board layout,
simultaneously switching outputs (SSOs) and their effects on sensitive asynchronous pins must be
considered.
Unused FF or I/O pins are tristated with weak pull-up. This default configuration applies to both
Flash*Freeze mode and normal operation mode. No user intervention is required.
Table 3-1 shows the Flash*Freeze pin location on the available packages for IGLOO and ProASIC3L
devices. The Flash*Freeze pin location is independent of device (except for a PQ208 package), allowing
migration to larger or smaller IGLOO devices while maintaining the same pin location on the board. Refer
to the "Flash*Freeze Technology and Low Power Modes" chapter of the IGLOO PLUS Device Family
User’s Guide for more information on I/O states during Flash*Freeze mode.
Table 3-1 Flash*Freeze Pin Location in IGLOO PLUS Devices
Package
Flash*Freeze Pin
CS281
W2
CS201
R4
CS289
U1
VQ128
34
VQ176
47
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