参数资料
型号: AGLP125V5-CS281
元件分类: FPGA
英文描述: FPGA, 3120 CLBS, 125000 GATES, PBGA281
封装: 10 X 10 MM, 1.05 MM HEIGHT, 0.5 MM PITCH, CSP-281
文件页数: 46/128页
文件大小: 4383K
代理商: AGLP125V5-CS281
IGLOO PLUS DC and Switching Characteristics
2- 10
R e v i sio n 1 1
Power Consumption of Various Internal Resources
Table 2-15 Different Components Contributing to Dynamic Power Consumption in IGLOO PLUS Devices
For IGLOO PLUS V2 or V5 Devices, 1.5 V Core Supply Voltage
Parameter
Definition
Device Specific Dynamic Power
(W/MHz)
AGLP125 AGLP060 AGLP030
PAC1
Clock contribution of a Global Rib
11.03
9.3
PAC2
Clock contribution of a Global Spine
0.81
0.41
PAC3
Clock contribution of a VersaTile row
0.81
PAC4
Clock contribution of a VersaTile used as a sequential module
0.11
PAC5
First contribution of a VersaTile used as a sequential module
0.057
PAC6
Second contribution of a VersaTile used as a sequential module
0.207
PAC7
Contribution of a VersaTile used as a combinatorial module
0.17
PAC8
Average contribution of a routing net
0.7
PAC9
Contribution of an I/O input pin (standard-dependent)
PAC10
Contribution of an I/O output pin (standard-dependent)
PAC11
Average contribution of a RAM block during a read operation
25.00
PAC12
Average contribution of a RAM block during a write operation
30.00
PAC13
Dynamic contribution for PLL
2.70
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