参数资料
型号: AM29BDS320GBD3VMF
厂商: SPANSION LLC
元件分类: PROM
英文描述: 2M X 16 FLASH 1.8V PROM, 70 ns, PBGA64
封装: 8 X 9 MM, 0.80 MM PITCH, FBGA-64
文件页数: 4/75页
文件大小: 1075K
代理商: AM29BDS320GBD3VMF
10
Am29BDS320G
27243B2 May 15, 2007
Data
Sheet
Input/Output Descriptions
A20-A0
=
Address inputs
DQ15-DQ0
=
Data input/output
CE#
=
Chip Enable input. Asynchronous relative to CLK for
the Burst mode.
OE#
=
Output Enable input. Asynchronous relative to CLK
for the Burst mode.
WE#
=
Write Enable input.
VCC
=
Device Power Supply
(1.65 – 1.95 V).
VIO
=
Input & Output Buffer Power Supply (either 1.65 –
1.95 V or 2.7 – 3.15 V).
VSS
=
Ground
NC
=
No Connect; not connected internally
RDY
=
Ready output; indicates the status of the Burst read.
Low = data not valid at expected time. High = data
valid.
CLK
=
CLK is not required in asynchronous mode. In burst
mode, after the initial word is output, subsequent
active edges of CLK increment the internal address
counter.
AVD#
=
Address Valid input. Indicates to device that the valid
address is present on the address inputs (A20–A0).
Low = for asynchronous mode, indicates valid
address; for burst mode, causes starting address to
be latched.
High = device ignores address inputs
RESET#
=
Hardware reset input. Low = device resets and
returns to reading array data
WP#
=
Hardware write protect input. At VIL, disables
program and erase functions in the two outermost
sectors. Should be at VIH for all other conditions.
ACC
=
At VID, accelerates programming; automatically
places device in unlock bypass mode. At VIL, locks all
sectors. Should be at VIH for all other conditions.
Logic Symbol
21
16
DQ15–DQ0
A20–A0
CE#
OE#
WE#
RESET#
CLK
RDY
AVD#
WP#
ACC
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