参数资料
型号: Am29F040B-70JC
厂商: Advanced Micro Devices, Inc.
英文描述: 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
中文描述: 4兆位(512亩× 8位)的CMOS 5.0伏只,统一部门快闪记忆体
文件页数: 2/30页
文件大小: 403K
代理商: AM29F040B-70JC
10
Am29F040B
P R E L I M I NARY
Note: See the appropriate Command Definitions table for
program command sequence.
Figure 1.
Program Operation
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does
not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. The Command
Definitions table shows the address and data require-
ments for the chip erase command sequence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored.
The system can determine the status of the erase
operation by using DQ7, DQ6, or DQ2. See “Write
Operation Status” for information on these status
bits. When the Embedded Erase algorithm is com-
plete, the device returns to reading array data and
addresses are no longer latched.
Figure 2 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to the Chip/Sector
Erase Operation Timings for timing waveforms.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un-
lock cycles, followed by a set-up command. Two addi-
tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. The Command Definitions table
shows the address and data requirements for the sec-
tor erase command sequence.
The device does
not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 s begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time be-
tween these additional cycles must be less than 50 s,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 s, the
system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence
and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7, DQ6, or DQ2.
Refer to “Write Operation Status” for information on
these status bits.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data?
No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
21445B-6
相关PDF资料
PDF描述
Am29F040B-70JE 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
Am29F040B-70JI 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
Am29F040B-70PCB 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
Am29F040B-70PC 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
Am29F040B-70PEB 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
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