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| 型号： | AM29F200BB-70SD |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:2Mbit; Package/Case:44-SOIC; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:70ns; Series:AM29 RoHS Compliant: Yes |
| 中文描述： | 128K X 16 FLASH 5V PROM, 70 ns, PDSO44 |
| 封装： | LEAD FREE, MO-180AA, SOP-44 |
| 文件页数： | 2/41页 |
| 文件大小： | 818K |
| 代理商： | AM29F200BB-70SD |
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8
Am29F200B
21526D5 March 3, 2009
D A TA
SH EE T
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state
machine. The state machine outputs dictate the func-
tion of the device. The appropr iate device bus
operations table lists the inputs and control levels
required, and the resulting output. The following sub-
sections describe each of these operations in further
detail.
Table 1.
Am29F200B Device Bus Operations
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note: See the sections Sector Group Protection and Temporary Sector Unprotect for more information.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the byte or word configura-
tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and con-
trolled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output
control and gates array data to the output pins. WE#
should remain at VIH. On x16 (word-wide) devices, the
BYTE# pin determines whether the device outputs
array data in words or bytes.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce
valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to the Read Operations Timings diagram for
the timing waveforms. ICC1 in the DC Characteristics
table represents the active current specification for
reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
On x16 (word-wide) devices, for program operations,
the BYTE# pin determines whether the device accepts
program data in bytes or words. Refer to “Word/Byte
Configuration” for more information.
Operation
CE#
OE#
WE#
RESET#
A0–A16
DQ0–DQ7
DQ8–DQ15
BYTE#
= VIH
BYTE#
= VIL
Read
L
H
AIN
DOUT
High-Z
Write
L
H
L
H
AIN
DIN
High-Z
CMOS Standby
VCC ± 0.5 V
X
VCC ± 0.5 V
X
High-Z
TTL Standby
H
X
H
X
High-Z
Output Disable
L
H
X
High-Z
Hardware Reset
X
L
X
High-Z
Temporary Sector Unprotect
(See Note)
XX
X
VID
AIN
DIN
X
相关PDF资料 |
PDF描述 |
|---|---|
| AM29F200BB-70SF | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:2Mbit; Package/Case:44-SOIC; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:70ns; Series:AM29 RoHS Compliant: Yes |
| AM29F200BB-90EC | Flash Memory IC; Access Time, Tacc:90ns; Package/Case:48-TSOP; Leaded Process Compatible:No; Memory Configuration:256K x 8; Peak Reflow Compatible (260 C):No; Supply Voltage Max:5.5V; Mounting Type:Surface Mount RoHS Compliant: No |
| AM29F200BB-90ED | Flash Memory IC; Memory Size:2Mbit; Memory Configuration:256K x 8; Package/Case:48-TSOP; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:90ns; Mounting Type:Surface Mount RoHS Compliant: Yes |
| AM29F200BB-90EF | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:2Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:90ns; Series:AM29 RoHS Compliant: Yes |
| AM29F200BB-90SD | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:2Mbit; Package/Case:44-SOIC; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:90ns; Series:AM29 RoHS Compliant: Yes |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AM29F200BB-70SE | 制造商:Spansion 功能描述:NOR Flash Parallel 5V 2Mbit 256K/128K x 8bit/16bit 70ns 44-Pin SOIC |
| AM29F200BB-70SF | 功能描述:闪存 2M (256KX8/128KX16) Parallel NOR Fl 5V RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| AM29F200BB-70SI\T | 制造商:Spansion 功能描述:NOR Flash Parallel 5V 2Mbit 256K/128K x 8bit/16bit 70ns 44-Pin SOIC T/R |
| AM29F200BB-90EC | 制造商:Advanced Micro Devices 功能描述: |
| AM29F200BB-90EF | 制造商:Advanced Micro Devices 功能描述: |
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