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| 型号： | AM29F400BT-90SC |
| 厂商： | ADVANCED MICRO DEVICES INC |
| 元件分类： | PROM |
| 英文描述： | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
| 中文描述： | 256K X 16 FLASH 5V PROM, 90 ns, PDSO44 |
| 封装： | MO-180AA, SOP-44 |
| 文件页数： | 7/37页 |
| 文件大小： | 238K |
| 代理商： | AM29F400BT-90SC |
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Am29F400B
7
P R E L I M I N A R Y
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the
inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1.
Am29F400B Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 12.0
±
0.5 V, X = Don’t Care, D
IN
= Data In, D
OUT
= Data Out, A
IN
= Address In
Note:
See the sections on Sector Protection and Temporary Sector Unprotect for more information.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the byte or word configura-
tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and control-
led by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are ac-
tive and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE# should
remain at V
IH
. The BYTE# pin determines whether the
device outputs array data in words or bytes.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory con-
tent occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the
device data outputs. The device remains enabled for
read access until the command register contents are
altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 9 for the timing diagram. I
CC1
in the
DC Characteristics table represents the active current
specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
IL
, and OE# to V
IH
.
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” for more in-
formation.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector ad-
dress” consists of the address bits required to uniquely
select a sector. The “Command Definitions” section
has details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
Operation
CE#
L
L
V
CC
±
0.5 V
H
L
X
OE#
L
H
WE#
H
L
RESET#
H
H
V
CC
±
0.5 V
H
H
L
A0–A17
A
IN
A
IN
DQ0–DQ7
D
OUT
D
IN
DQ8–DQ15
BYTE#
= V
IH
D
OUT
D
IN
BYTE#
= V
IL
High-Z
High-Z
Read
Write
CMOS Standby
X
X
X
High-Z
High-Z
High-Z
TTL Standby
Output Disable
Hardware Reset
Temporary Sector Unprotect
(See Note)
X
H
X
X
H
X
X
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
X
X
X
V
ID
A
IN
D
IN
D
IN
High-Z
相关PDF资料 |
PDF描述 |
|---|---|
| Am29F400BT-90SCB | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
| AM29F400BT-90SE | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
| AM29F400BT-90SEB | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
| AM29F400BT-90SI | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
| Am29F400BT-90SIB | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AM29F400BT-90SE\T | 制造商:Spansion 功能描述:4 MEGABIT (512 K X 8-BIT/256 K X 16-BIT) CMOS 5.0 VOLT-ONLY BOOT SECTOR FLASH MEMORY |
| AM29F400BT-90SF\\T | 制造商:Spansion 功能描述:NOR Flash Parallel 5V 4Mbit 512K/256K x 8bit/16bit 90ns 44-Pin SO T/R |
| AM29F400BT-90SF\T | 制造商:Spansion 功能描述:NOR Flash Parallel 5V 4Mbit 512K/256K x 8bit/16bit 90ns 44-Pin SO T/R |
| AM29F400BT-90SI | 制造商:Spansion 功能描述: |
| AM29F800BB-120DPC1 | 制造商:Spansion 功能描述:5V 8M FLASH KNOWN GOOD DIE W/BOTTOM BOOT (COMMERCIAL TEMP) - Gel-pak, waffle pack, wafer, diced wafer on film |
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