SPRS550C
– OCTOBER 2009 – REVISED MARCH 2011
Table 6-6. GPMC/NOR Flash Interface Asynchronous Timing
– Internal Parameters(1) (2) (continued) NO.
PARAMETER
1.8V,3.3V
UNIT
MIN
MAX
FI7
Maximum output enable generation delay from internal functional clock
6.5
ns
FI8
Maximum write enable generation delay from internal functional clock
6.5
ns
FI9
Maximum functional clock skew
100
ps
Table 6-7. GPMC/NOR Flash Interface Timing Requirements
– Asynchronous Mode
NO.
PARAMETER
1.8V,3.3V
UNIT
MIN
MAX
FA5(1)
tacc(DAT)
Data maximum access time
H(2)
GPMC_FCLK cycles
FA20(3)
tacc1-pgmode(DAT)
Page mode successive data maximum
P(4)
GPMC_FCLK cycles
access time
FA21(5)
tacc2-pgmode(DAT)
Page mode first data maximum access
H(2)
GPMC_FCLK cycles
time
(1)
The FA5 parameter illustrates the amount of time required to internally sample input Data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after FA5 functional clock cycles, input Data is internally sampled by active functional clock
edge. FA5 value must be stored inside the AccessTime register bit field.
(2)
H = AccessTime * (TimeParaGranularity + 1)
(3)
The FA20 parameter illustrates amount of time required to internally sample successive input Page Data. It is expressed in number of
GPMC functional clock cycles. After each access to input Page Data, next input Page Data is internally sampled by active functional
clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.
(4)
P = PageBurstAccessTime * (TimeParaGranularity + 1)
(5)
The FA21 parameter illustrates amount of time required to internally sample first input Page Data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, First input Page Data is internally sampled by
active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.
Table 6-8. GPMC/NOR Flash Interface Switching Characteristics
– Asynchronous Mode
NO.
PARAMETER
1.8V/ 3.3V
UNIT
MIN
MAX
tR(DO)
Rise time, output data
2.0
ns
tF(DO)
Fall time, output data
2.0
ns
FA0
tW(nBEV)
Pulse duration,
Read
ns
gpmc_nbe0_cle,
Write
ns
gpmc_nbe1 valid time
FA1
tW(nCSV)
Pulse duration,
Read
ns
Write
ns
FA3
td(nCSV-nADVIV)
Delay time,
Read
– 0.2
ns
Write
– 0.2
ns
gpmc_nadv_ale invalid
FA4
td(nCSV-nOEIV)
– 0.2
ns
gpmc_noe invalid (Single read)
FA9
td(AV-nCSV)
Delay time, address bus valid to
– 0.2
ns
FA10
td(nBEV-nCSV)
Delay time, gpmc_nbe0_cle,
– 0.2
ns
valid
FA12
td(nCSV-nADVV)
– 0.2
ns
gpmc_nadv_ale valid
FA13
td(nCSV-nOEV)
– 0.2
ns
gpmc_noe valid
FA14
td(nCSV-IODIR)
– 0.2
ns
gpmc_io_dir high
FA15
td(nCSV-IODIR)
– 0.2
ns
gpmc_io_dir low
FA16
tw(AIV)
Address invalid duration between 2
ns
successive R/W accesses
118
TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS
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2009–2011, Texas Instruments Incorporated