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| 型号： | AM79Q021JC |
| 厂商： | ADVANCED MICRO DEVICES INC |
| 元件分类： | 编解码器 |
| 英文描述： | PCM CODEC, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 25/64页 |
| 文件大小： | 911K |
| 代理商： | AM79Q021JC |
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SLAC Products
31
Real-Time Data Register Operation
To obtain time-critical data such as off/on-hook and
ring trip information from the SLIC with a minimum of
processor time and effort, the QSLAC device contains
an 8-bit Real Time Data register. This register contains
CDA and CDB bits from all four channels. The CDA bit
for each channel is a debounced version of the CD1
input. The CDA bit is normally used for switchhook.
The CDB bit for each channel normally contains the
CD2 input bit; however, if the E1 multiplex operation is
enabled, the CDB bit will contain the debounced value
of the CD1B bit. CD1 and CD2 can be assigned to off-
hook, ring trip, ground key signals, or other signals.
Frame sync is needed for the debounce and the
ground key signals. If Frame sync is not provided, the
real-time register will not work. The register is read
using MPI Commands 16 and 17 (4D/4Fh), and may
be read at any time regardless of the state of the
Channel Enable Register. This allows off/on-hook, ring
trip, or ground key information for all four channels to
be obtained from the QSLAC device with one read
operation versus one read per channel. If these data
bits are not used for supervision information, they can
be accessed on an individual channel basis in the
same way as C3–C5; however, CD1 and CD1B will not
be debounced.
Interrupt
In addition to the Real Time Data register, an interrupt
signal has been implemented in the QSLAC device.
The interrupt signal is an active Low output signal
which pulls Low whenever the unmasked CD bits
change state (Low to High or High to Low); or
whenever the transmit PCM data changes on a
channel in which the Arm Transmit Interrupt (ATI) bit is
on. The interrupt control is shown in Figure 9. The
interrupt remains Low until the appropriate register is
read. This output can be programmed as TTL or open
drain. When an interrupt is generated, all of the
unmasked bits in the Real Time Data register latch and
remain latched until the interrupt is cleared. The
interrupt is cleared by reading the register with
Command 17, by writing to the interrupt mask register
(Command 26), or by a reset. If any of the inputs to the
unmasked bits in the Real Time Data register are
different from the register bits when the interrupt is
cleared, a new interrupt is immediately generated with
the new data latched into the Real Time Data register.
For this reason, the interrupt logic in the controller
should be level-sensitive rather than edge-sensitive.
Interrupt Mask Register
The Real Time Data register data bits can be masked
from causing an interrupt to the processor using the
interrupt mask register. The mask register can be
written or read via the MPI Commands 26 and 27.
Active State
Each channel of the QSLAC device can operate in
either the Active (operational) or Inactive (standby)
state. In the Active state, individual channels of the
QSLAC device can transmit and receive PCM or linear
data and analog information. The Active state is
required when a telephone call is in progress. The
activate command (MPI Command 5), puts the
selected channel(s) into this state (see channel enable
register). Bringing a channel of the QSLAC device into
the Active state is only possible through the MPI.
Inactive State
All channels of the QSLAC device are forced into the
Inactive (standby) state by a power-up or hardware
reset. Individual channels can be programmed into
this state by the deactivate command (Command 1) or
by the software reset command (Command 2). Power
is disconnected from all nonessential circuitry while
the MPI remains active to receive commands. The
analog output is tied to VREF through a resistor whose
value depends on the VMODE bit. All circuits that
contain programmed information retain their data in
the Inactive state.
Low Power State
If the Low Power state is turned on by setting LPM = 1
(Command 14), the internal clock speed substantially
reduces when all four channels are deactivated. When
this happens, the CFAIL bit is set to 1, and if MCLK
also is lost, the microprocessor interface requires a
minimum of 75 ms off time between commands.
Chopper Clock
On the Am79Q02JC there is a chopper clock output to
drive the switching regulator on some AMD SLICs. The
clock frequency is selectable as 256 or 292.57 kHz by
the CHP bit (Command 12). The chopper output must
be turned on with the ECH bit (Command 45).
Reset States
The QSLAC device can be reset by application of
power, by an active Low on the hardware Reset pin
(RST), by a hardware reset command, or by CS Low
for 16 or more rising edges of DCLK. This resets the
QSLAC device to the following state:
1. A-law companding is selected.
2. Default B, X, R, and Z filter values are selected and
the AISN is set to zero.
3. Default digital gain blocks (GX, GR) are selected.
The analog gains, AX and AR, are set to 0 dB.
4. SLIC I/Os (CD1–C5) are set to the Input state.
5. All of the test states in the Operating Conditions
register are turned off (0’s).
6. All four channels are in the Inactive (standby) state.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AM79Q021JC/T | 制造商:Advanced Micro Devices 功能描述: |
| AM79Q021VC | 制造商:Advanced Micro Devices 功能描述: |
| AM79Q02JC | 制造商:Advanced Micro Devices 功能描述: |
| AM79Q031 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Quad Subscriber Line Audio-Processing Circuit (QSLAC) Devices |
| AM79Q031JC | 制造商:Advanced Micro Devices 功能描述: |
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