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| 型号： | AM79Q021JC |
| 厂商： | ADVANCED MICRO DEVICES INC |
| 元件分类： | 编解码器 |
| 英文描述： | PCM CODEC, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 63/64页 |
| 文件大小： | 911K |
| 代理商： | AM79Q021JC |
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8
Am79Q02/021/031 Data Sheet
PIN DESCRIPTIONS
Pin Names
Type
Description
CD11–CD14,
CD21–CD24
Inputs/Outputs
Control and Data. CD1 and CD2 are TTL compatible programmable Input or Output (I/O)
ports. They can be used to monitor or control the state of SLIC or any other device associ-
ated with subscriber line interface. The direction, input or output, is programmed using MPI
Command 22. As outputs, CD1 and CD2 can be used to control relays, illuminate LEDs, or
perform any other function requiring a latched TTL compatible signal for control. The output
state of CD1 and CD2 is written using MPI Command 20. As inputs, CD1 and CD2 can be
processed by the QSLAC device (if programmed to do so). CD1 can be debounced before
it is made available to the system. The debounce time is programmable from 0 to 15 ms in
1 ms increments using MPI Command 45. CD2 can be filtered using the up/down counter
facility and programming the sampling interval using MPI Command 52.
Additionally, CD1 can be demultiplexed into two separate inputs using the E1 demultiplexing
function. The E1 demultiplexing function of the QSLAC device was designed to interface di-
rectly to AMD SLICS supporting the ground key function. With the proper AMD SLIC and the
E1 function of the QSLAC enabled, the CD1 bit can be demultiplexed into an Off-Hook/Ring
Trip signal and Ground Key signal. In the demultiplex mode, the second bit, Ground Key, takes
the place of the CD2 as an input. The demultiplexed bits can be debounced (CD1) or filtered
(CD2) as explained previously. A more complete description of CD1, CD2, debouncing, and
filtering functions is contained in the Operating the QSLAC Device section on page 25.
Once the CD1 and CD2 inputs are processed (Debounced, Filtered and/or Demultiplexed)
by the QSLAC device, the information can be accessed by the system in two ways: 1) on a
per channel basis along with C3, C4, and C5 of the specific channel using MPI Command
21, or 2) by using MPI Commands 16 and 17, which obtain the CD1 and CD2 bits from all
four channels simultaneously. This feature reduces the processor overhead and the time re-
quired to retrieve time-critical signals from the line circuits, such as off-hook and ring trip.
With this feature, hookswitch status and ring trip information, for example, can be obtained
from all four channels of a QSLAC device with one read command.
C31–C34,
C41–C44,
C51–C54
Inputs/Outputs
Control. C3, C4, and C5 are TTL-compatible programmable Input or Output (I/O) ports. They
can be used to monitor or control the state of SLIC or any other device associated with sub-
scriber line interface. The direction, input or output, is programmed using MPI Command 22.
As outputs, C3, C4, and C5 can be used to control relays, illuminate LEDs, or perform any
other function requiring a latched TTL compatible signal for control. The output state of C3,
C4, and C5 is written using MPI Command 20. As inputs, C3, C4, and C5 can be accessed
by the system by using MPI Command 21.
The Am79Q021 QSLAC device contains a single PCM highway and five programmable I/Os
per channel (CD1, CD2, C3, C4, and C5) in a 44-pin PLCC or TQFP package. In the
Am79Q02 QSLAC device, the C51, C52, C53, and C54 I/Os are eliminated, enabling dual
PCM highways and a chopper clock output in a 44-pin PLCC or TQFP package. In the
Am79Q031 QSLAC device, the C31–C51, C32–C52, C33–C53, and C34–C54 I/Os are elim-
inated, enabling a single PCM highway and two control and data I/Os (CD1, CD2) per chan-
nel in a 32-pin PLCC package.
CHCLK
Output
Chopper Clock. This output provides a 256 kHz or a 292.57 kHz, 50% duty cycle, TTL-com-
patible clock for use by up to four SLICs with built-in switching regulators. The CHCLK fre-
quency is synchronous to MCLK, but the phase relationship to MCLK is random. The chopper
clock is not available in all package types.
CS
Input
Chip Select. The Chip Select input (active Low) enables the device so that control data can
be written to or read from the part. The channels selected for the write or read operation are
enabled by writing 1 s to the appropriate bits in the Channel Enable Register of the QSLAC
device prior to the command. See EC1, EC2, EC3, and EC4 of the Command 14, page 42,
for more information. If Chip Select is held Low for 16 rising edges of DCLK, a hardware re-
set is executed when Chip Select returns High.
DCLK
Input
Data Clock. The Data Clock input shifts data into and out of the microprocessor interface of
the QSLAC device. The maximum clock rate is 4.096 MHz.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AM79Q021JC/T | 制造商:Advanced Micro Devices 功能描述: |
| AM79Q021VC | 制造商:Advanced Micro Devices 功能描述: |
| AM79Q02JC | 制造商:Advanced Micro Devices 功能描述: |
| AM79Q031 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Quad Subscriber Line Audio-Processing Circuit (QSLAC) Devices |
| AM79Q031JC | 制造商:Advanced Micro Devices 功能描述: |
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