SLAC Products
67
s An inactive (high) MX and MR pair bit for two or more
consecutive frames shows an idle state on the
monitor channel and the end of message (EOM).
s
Figure 17 shows that transmission is initiated by the
transition of the transmitter MX bit from the inactive
to the active state. The transition coincides with the
beginning of the first byte sent on the monitor
channel. The receiver acknowledges the first byte
by setting MR bit to active and keeping it active for
at least one more frame.
s The same byte is sent continuously in each of the
succeeding frames until either a new byte is
transmitted, the end of message, or an abort.
s Any false MX or MR bit received by the receiver
or transmitter leads to a request for abort or an
abort, respectively.
s The same data must be received in two consecutive
frames in order to be accepted by the receiver.
s A bus collision resolution mechanism is
implemented in the transmitter. Before a device can
send a monitor channel message, it must detect the
idle condition (MR and MX both high).
s Any abort command leads to a reset of any pending
commands in the QSLAC device. The device
remains in the previous configuration and is ready
to receive a new command.
s For maximum data transfer speed, the transmitter
anticipates the falling edge of the receiver’s
the operation of the monitor transmitter and receiver
sections in the QSLAC device.
MR
MXR
MR
MXR
Idle
MX = 1
1st Byte
MX = 0
nth Byte
ACK, MX = 1
Wait for
ACK, MX = 0
Wait
MX = 1
Abort
MX = 1
EOM
MX = 1
MR: MR bit received
MR: MR bit calculated and expected on the DU line
MXR: MX - bit sampled on the DU line
MR
RQT
MR
RQT
MR
RQT
MR
RQT
MR
RQT
MR + MXR
MR
MXR
Initial
State
Any State
CLS/ABT
Figure 18. Monitor Transmitter State Diagram
21108A-032
CLS: Collision within the monitor byte
RQT: Request for transmission from internal source
ABT: Abort request/indication