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参数资料
| 型号： | AN-90 |
| 厂商： | Fairchild Semiconductor Corporation |
| 英文描述： | 74C Family Characteristics |
| 中文描述： | 74C条家庭特征 |
| 文件页数： | 5/7页 |
| 文件大小： | 209K |
| 代理商： | AN-90 |
fanout for the 4000 series while 54C/74C has a fanout of
40 pF.Afanout of 5 pF (one gate input) is all but useless, and
specified propagation delay would most probably not be re-
alized in an actual system.
Operating at loads other than 50 pF poses a problem since
propagation is a function of load capacitance. To simplify the
problem Figure 7 has been generated and gives the slope of
the propagation delay vs load capacitance line (
t
/pF) as a
function of power supply voltage. Because the propagation
delay for zero load capacitance is not zero and depends on
the internal structure of each device, an offset term must be
added that is unique to a particular device type. Since each
data sheet gives propagation delay for 50 pF the actual de-
lay for different loads can be computed with the aid of the fol-
lowing equation:
As an example let’s compute the propagation delay for an
MM74C00 driving 15 pF load and operating with a
V
CC
= 5.0V. The equation gives:
The same formula and curves may be applied to more com-
plex devices. For example the propagation delay from data
to output for an MM74C157 operating at V
CC
= 10V and C
L
= 100 pF is:
It is significant to note that this equation and Figure 7 apply
to all 54C/74C devices. This is true because of the close
match in drive characteristics of every device including MSI
functions, i.e., the slope of the propagation delay vs load ca-
pacitance line at a given voltage is typically equal for all de-
vices. The only exception is high fan-out buffers which have
a smaller
t
pd
/pF.
Another point to consider in the design of a CMOS system is
the effect of power supply voltage on propagation delay. Fig-
ure 8 shows propagation delay as a function of V
CC
and
propagation delay times power consumption vs V
for an
MM74C00 operating with 50 pF load at f = 100 kHz.
Above V
= 5.0V note the speed power product curve ap-
proaches a straight line. However the t
pd
curve starts to “flat-
ten out”. Going from V
= 5.0V to V
= 10V gives a 40%
decrease in propagation delay and going from V
= 10V to
V
= 15V only decreases propagation delay by 25%.
Clearly for V
>
10V a small increase in speed is gained by
a disproportionate increase in power. Conversely, for small
decreases in power below V
CC
= 5.0V large increases in
propagation delay result.
Obviously it is optimum to use the lowest voltage consistent
with system speed requirements. However, in general it can
be seen from Figure 8 that the best speed power perfor-
mance will be obtained in the V
CC
= 5.0V to V
CC
= 10V
range.
AN006021-10
FIGURE 7. Typical Propagation Delay per pF of Load
Capacitance vs Power Supply
AN006021-11
FIGURE 8. Speed Power Product and
Propagation Delay vs V
CC
5
www.fairchildsemi.com
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