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参数资料
| 型号： | AN1568D |
| 厂商： | ON SEMICONDUCTOR |
| 英文描述： | Interfacing Between LVDS and ECL |
| 中文描述： | 接口之间的LVDS和ECL |
| 文件页数： | 2/10页 |
| 文件大小： | 88K |
| 代理商： | AN1568D |
AN1568/D
http://onsemi.com
2
Table 1. MC100EXXX/MC100ELXXX/LVELXXX/EPXXX/LVEPXXX
(T
A
= 0
°
C to +85
°
C)
Symbol
Parameter
2.5 V LVPECL
(Note 1)
3.3 V LVPECL
(Note 1)
5.0 V PECL
(Note 1)
NECL
Unit
V
CC
Positive Supply Voltage
+2.5
+3.3
+5
GND
V
V
EE
Negative Supply Voltage
GND
GND
GND
5.2, 4.5, 3.3 or 2.5
V
V
OH
Maximum Output HIGH Level
1.680
2.480
4.180
0.820
V
V
OH
Typical Output HIGH Level
1.555
2.355
4.055
0.945
V
V
OH
Minimum Output HIGH Level
1.430
2.230
3.930
1.070
V
V
OL
Maximum Output LOW Level
0.880
1.680
3.380
1.620
V
V
OL
Typical Output LOW Level
0.755
1.555
3.255
1.745
V
V
OL
Minimum Output LOW Level
0.630
1.430
3.130
1.870
V
1. All levels vary 1:1 with V
CC
and loaded with 50 to V
CC
2.0 V.
LVDS Levels
As the name indicates, the LVDS main attribute is the low
voltage amplitude levels compared to other data
transmission standards, as shown in Figure 1. The LVDS
specification states 250 mV to 400 mV output swing for
driver/transmitter (V
OUTPP
). The low voltage swing levels
result in low power consumption while maintaining high
performance levels required by most users. In addition,
LVDS uses differential data transmission technology
equivalent to ECL. Furthermore, LVDS technology is not
dependent on specific power supply levels like ECL
technology. This signifies an easy migration path to lower
supply voltages such as 3.3 V, 2.5 V, or lower voltages while
still maintaining the same signaling levels and high
performance. ON Semiconductor currently provides a 2.5 V
1:5 dual differential LVDS Clock Driver/Receiver
(MC100EP210S).
Figure 1. Comparison of Output Voltage Levels
Standards (Figure not to Scale)
PECL
3.3 V LVPECL
NECL/LVNECL
LVDS
2.5 V LVPECL
3.3 V LVTTL/LVCMOS
S
LVDS require a 100
differential outputs to generate the Differential Output
Voltage (V
OD
) with a maximum current of 2.5 mA flowing
through the load resistor. This load resistor will terminate the
50 controlled characteristic impedance line, which
prevent reflections and reduces unwanted electromagnetic
emission (Figure 2).
load resistor between the
Figure 2. LVDS Output Definition
LVDS
Z = 50
Z = 50
100
LVDS receivers require 200 mV minimum input swing
within the input voltage range of 0 V to 2.4 V and can tolerate
a minimum of
1.0 V ground shift between the driver’s
ground and the receiver’s ground, since LVDS receivers
have a typical driver offset voltage of 1.2 V. The common
mode range of the LVDS receiver is 0.2 V to 2.2 V, and the
recommended LVDS receiver input voltage range is from
0 V to 2.4 V. Common mode range of LVDS is similar to the
theory of Voltage Input HIGH Common Mode Range
(V
IHCMR
) of ECL devices.
Currently more LVDS standards are being developed as
LVDS technology gains in popularity.
BLVDS
Bus LVDS (BLVDS) was developed for multipoint
applications. This standard is targeted at heavily loaded back
planes, which reduces the impedance of the transmission
line by 50% or more. By providing increased drive current,
the double termination seen by the driver will be
compensated.
MLVDS
TIA TR30.2 standards group is developing another
multipoint LVDS application called Multipoint LVDS
(MLVDS). The maximum data rate is 500 Mbps.
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