参数资料
| 型号： | AP9050FDB-7 |
| 厂商： | Diodes Inc |
| 文件页数： | 4/9页 |
| 文件大小： | 0K |
| 描述： | IC PMIC INTERFACE PROT UDFN2020 |
| 标准包装： | 1 |
| 应用： | 便携式设备 |
| 电流 - 电源： | 110µA |
| 电源电压： | 3 V ~ 30 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-UDFN 裸露焊盘 |
| 供应商设备封装： | 6-UDFN2020（2x2） |
| 包装： | 标准包装 |
| 其它名称： | AP9050FDB-7DIDKR |
AP9050
PROTECTION INTERFACE for PMICs with
INTEGRATED OVP CONTROL
Electrical Characteristics (V IN (OVP_SENSE) = 5.0V, T J = +25°C, unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
Typ.
Max
Unit
Power FET
I DSS
I GSS
Zero Gate Voltage Drain Current
Gate-to-Source Leakage Current
V DS = 24V, V GS = 0V
T J = 85 ° C
V DS = 0V, V GS = ±8V
1.0
10
80
μA
nA
V GS(th)
R DS(on)
g FS
C ISS
C OSS
C RSS
Gate Threshold Voltage
Drain-to-Source On-Resistance
(Note 7)
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V GS = V DS , I D = 250μA
V GS = 4.5V, I D = 2.0A
V GS = 2.5V, I D = 2.0A
V DS = 5V, ID = 2.0A
V DS = 15V, V GS = 0V,
f = 1MHz
V DS = 15V, V GS = 0V,
f = 1MHz
V DS = 15V, V GS = 0V,
f = 1MHz
0.62
0.9
41
55
8
500
65
50
1.2
53
68
V
m ?
S
pF
pF
pF
LDO (unless otherwise noted, T J = 25oC, V IN = 5.0V)
V OUT
V head
Regulated Output Voltage
Headroom
V IN = 5.5V, I OUT = 1mA
V IN ? V OUT , I OUT = 1.2mA,
V IN = 4.6V
V IN ? V OUT , I OUT = 10mA,
V IN = 4.8V, T J = ? 40 to +125 ° C
4.6
5.0
5.3
150
1000
V
mV
mV
Response to Input Transient
t pulse
V pk
Time signal is above 5.5V
Peak Voltage
V IN 0 to 30V, < 1μs rise time,
5.0k ? resistive load (Note 8)
V IN 0 to 30V, < 1μs rise time,
5.0k ? resistive load (Note 8)
5.0
9.0
μs
V
Total Device
I bias
V IN_min
Input Bias Current
Minimum Operating Voltage
V IN = 5.5V
110
850
3.0
μA
V
Notes:
7. Pulse test width 300μs, duty cycle 2%
8. Guaranteed by design
AP9050
Document number: DS35283 Rev. 1 - 2
4 of 9
March 2011
? Diodes Incorporated
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