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参数资料
型号： APA150-PQ208I
厂商： Microsemi SoC
文件页数： 106/178页
文件大小： 0K
描述： IC FPGA PROASIC+ 150K 208-PQFP
标准包装： 24
系列： ProASICPLUS
RAM 位总计： 36864
输入/输出数： 158
门数： 150000
电源电压： 2.3 V ~ 2.7 V
安装类型： 表面贴装
工作温度： -40°C ~ 85°C
封装/外壳： 208-BFQFP
供应商设备封装： 208-PQFP（28x28）
ProASICPLUS Flash Family FPGAs
v5.9
2-23
Note: Each RAM block contains a multiplexer (called DMUX) for each output signal, increasing design efficiency. These DMUX cells do not
consume any core logic tiles and connect directly to high-speed routing resources between the RAM blocks. They are used when
RAM blocks are cascaded and are automatically inserted by the software tools.
Figure 2-19 Basic FIFO Block Diagrams
Table 2-15 Memory Block FIFO Interface Signals
FIFO Signal
Bits
In/Out
Description
WCLKS
1
In
Write clock used for synchronization on write side
RCLKS
1
In
Read clock used for synchronization on read side
LEVEL <0:7>
8
In
Direct configuration implements static flag logic
RBLKB
1
In
Read block select (active Low)
RDB
1
In
Read pulse (active Low)
RESET
1
In
Reset for FIFO pointers (active Low)
WBLKB
1
In
Write block select (active Low)
DI<0:8>
9
In
Input data bits <0:8>, <8> will be generated parity if PARGEN is true
WRB
1
In
Write pulse (active Low)
FULL, EMPTY
2
Out
FIFO flags. FULL prevents write and EMPTY prevents read
EQTH, GEQTH
2
Out
EQTH is true when the FIFO holds the number of words specified by the LEVEL signal.
GEQTH is true when the FIFO holds (LEVEL) words or more
DO<0:8>
9
Out
Output data bits <0:8>. <8> will be parity output if PARGEN is true.
RPE
1
Out
Read parity error (active High)
WPE
1
Out
Write parity error (active High)
LGDEP <0:2>
3
In
Configures DEPTH of the FIFO to 2 (LGDEP+1)
PARODD
1
In
Parity generation/detect – Even when Low, odd when High
FIFO
(256x9)
LEVEL<0:7>
DO <0:8>
DI<0:8>
WRB
RDB
WBLKB
RBLKB
RPE
PARODD
WPE
LGDEP<0:2>
FULL
EMPTY
EQTH
GEQTH
WCLKS
RCLKS
RESET
RPE
WPE
FULL
EMPTY
EQTH
GEQTH
DO <0:8>
RPE
WPE
FULL
EMPTY
EQTH
GEQTH
DI <0:8>
DO <0:8>
LEVEL <0:7>
WRB
RDB
WBLKB
RBLKB
RPE
PARODD
WPE
LGDEP<0:2>
DI <0:8>
LEVEL <0:7>
WRB
RDB
WBLKB
RBLKB
PARODD
LGDEP<0:2>
FULL
EMPTY
EQTH
GEQTH
RCLKS
RESET
LEVEL<0:7>
DI<0:8>
WRB
RDB
WBLKB
RBLKB
PARODD
LGDEP<0:2>
WCLKS
DO <0:8>
FIFO
(256x9)
FIFO
(256x9)
FIFO
(256x9)
Sync Write
and
Sync Read
Ports
Sync Write
and
Async Read
Ports
Async Write
and
Sync Read
Ports
Async Write
and
Async Read
Ports
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相关代理商/技术参数
参数描述
APA150-PQ896A 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Automotive-Grade ProASIC Flash Family FPGAs
APA150-PQB 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
APA150-PQES 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
APA150-PQG208 功能描述:IC FPGA PROASIC+ 150K 208-PQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASICPLUS 标准包装:90 系列:ProASIC3 LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:36864 输入/输出数:157 门数:250000 电源电压:1.425 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 125°C 封装/外壳:256-LBGA 供应商设备封装:256-FPBGA（17x17）
APA150-PQG208A 功能描述:IC FPGA PROASIC+ 150K 208-PQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASICPLUS 标准包装:90 系列:ProASIC3 LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:36864 输入/输出数:157 门数:250000 电源电压:1.425 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 125°C 封装/外壳:256-LBGA 供应商设备封装:256-FPBGA（17x17）
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