参数资料
型号: APEK4986SLP-01-T
厂商: Allegro Microsystems Inc
文件页数: 1/17页
文件大小: 0K
描述: Board Eval Motor Control A4986
标准包装: 1
主要目的: 电源管理,电机控制,步进控制器
嵌入式:
已用 IC / 零件: A4986
已供物品:
相关产品: 620-1342-2-ND - IC PWM MOTOR DRIVER 24TSSOP
其它名称: 620-1376
A4986
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
Features and Benefits
Description
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Low R DS(ON) outputs
Internal mixed current decay mode
Synchronous rectification for low power dissipation
Internal UVLO
Crossover-current protection
3.3 and 5 V compatible logic supply
Thin profile QFN and TSSOP packages
Thermal shutdown circuitry
Short-to-ground protection
Shorted load protection
Low current Sleep mode, < 10 μ A
The A4986 is a dual DMOS full-bridge stepper motor driver
with parallel input communication and overcurrent protection.
Each full-bridge output is rated up to 35 V and ±2 A.
The A4986 includes fixed off-time pulse width modulation
(PWM) current regulators, along with 2- bit nonlinear DACs
(digital-to-analog converters) that allow stepper motors to be
controlled in full, half, and quarter steps. The PWM current
regulator uses the Allegro ? patented mixed decay mode for
reduced audible motor noise, increased step accuracy, and
reduced power dissipation.
Internal synchronous rectification control circuitry is provided
Packages :
to improve power dissipation during PWM operation.
24-contact QFN
4 mm × 4 mm × 0.75 mm
(ES package)
24-pin TSSOP
with exposed thermal pad
(LP Package)
Approximate size
The outputs are protected from shorted load and short-to-
ground events, which protect the driver and associated circuitry
from thermal damage or flare-ups. Other protection features
include thermal shutdown with hysteresis, undervoltage lockout
(UVLO) and crossover current protection. Special power-up
sequencing is not required.
The A4986 is supplied in a 24-contact QFN package (ES), and
a 24-pin TSSOP package (LP) with an overall package height
of ≤ 1.2 mm. Both packages have exposed pads for enhanced
thermal dissipation, and are lead (Pb) free (suffix –T), with
100% matte tin plated leadframes.
Typical Application Diagram
V DD
0.22 μ F
0.1 μ F
0.1 μ F
0.22 μ F
VREG ROSC
CP1
CP2
VCP
VBB1
VDD
VBB2
100 μ F
Microcontroller or
Controller Logic
SLEEP
IN01
IN02
A4986
OUT1A
OUT1B
SENSE1
PH1
IN11
IN12
PH2
OUT2A
OUT2B
VREF
GND
GND
SENSE2
4986-DS, Rev. 4
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APEK4985SLP-01-T Board Eval Motor Control A4985
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