Copyright
ANPEC Electronics Corp.
Rev. A.4 - May., 2005
APL5913
www.anpec.com.tw
14
Feedback Network (Cont.)
Application Information (Cont.)
Select a proper R1(selected) to be a little larger
than the calculated R1.
- Calculate the C1 as the following :
Where R1=R1(selected)
Select a proper C1(selected) to be a little smaller
than the calculated C1.
- The C1 calculated from equation (4) must meet
the following equation:
Where R1=R1(calculated) from equation (3)
If the C1(calculated) can not meet the equation
(5), please use the Condition 3.
- Use equation (2) to calculate the R2.
Condition 3 : Low ESR (eg. Ceramic Capacitors)
- Calculate the R1 as the following:
Select a proper R1(selected) to be a little larger
than the calculated R1.
The minimum selected
R1 is equal to 1k
W
when the calculated R1 is
smaller than 1k or negative.
- Calculate the C1 as the following :
Where R1=R1(selected)
Select a proper C1(selected) to be a little smaller
than the calculated C1.
- The C1 calculated from equation (7) must meet
the following equation :
V
1.25
0.033
C1
)
(k
Where R1=R1(calculated) from equation (6)
If the C1
(calculated)
can not meet the equation (8),
please use the Condition 2.
- Use equation (2) to calculate the R2.
The reason to have three conditions described above
is to optimize the load transient responses for all kinds
of the output capacitor. For stability only, the Condition
2, regardless of equation (5), is enough for all kinds of
output capacitor.
[
]
(4)
........
R1
C
101
ESR
0.71
C1
)
(k
OUT(uF)
)
(m
(pF)
+
=
(5)
R1
V
37.5
1
ESR
143
1
7.2
C1
)
(k
OUT(V)
)
(m
(pF)
+
≥
(6)
V
37.5
C
300)
ESR
(2.1
R1
OUT(V)
OUT(uF)
)
(m
)
(k
+
=
(7)
R1
V
37.5
1
C
34.2)
ESR
(0.24
C1
)
(k
OUT(V)
OUT(uF)
)
(m
(pF)
+
+
=
(8)
C
ESR
R1
OUT(uF)
)
(m
OUT(V)
(pF)
+
≥
PCB Layout Considerations (See Figure 2)
1. Please solder the Exposed Pad and VIN together
on the PCB. The main current flow is through the
exposed pad. Refer Figure 3 to make a proximate
topology.
2. Please place the input capacitors for VIN and
VCNTL pins near pins as close as possible.
3. Ceramic decoupling capacitors for load must be
placed near the load as close as possible.
4. To place APL5913 and output capacitors near the
load is good for performance.
5. The negative pins of the input and output capaci-
tors and the GND pin of the APL5913 are connected
to the ground plane of the load.
6. Please connect PIN 3 and 4 together by a wide
track.
7. Large current paths must have wide tracks.
8. See the Typical Application
(see next page Figure 2)
- Connect the one pin of the R2 to the GND of
APL5913
- Connect the one pin of R1 to the Pin 3 of APL5913
- Connect the one pin of C1 to the Pin 3 of APL5913