参数资料
型号: APT7843
厂商: Anpec Electronics Corporation
英文描述: Touch Screen Controller
中文描述: 触摸屏控制器
文件页数: 18/18页
文件大小: 622K
代理商: APT7843
Copyright ANPEC Electronics Corp.
Rev. A.8 - Apr., 2002
APT7843
www.anpec.com.tw
9
Single-Ended reference mode
Figure 3 shows the diagram of single-ended refer-
ence mode.
This application shows the measurement of current
Y poisition is made by connecting the X+ input to the
A/D converter, turning on the Y+ and Y- drivers, and
digitizing the voltage on X+ . For this measurement,
the resistance in the X+ lead does not affect the con-
version. However, since the resistance between Y+
and Y- is fairly low, the on-resistance of the Y drivers
does make a small difference. Under the situation out-
lined so far, it would not be possible to achieve a zero
volt input or a full-scale input regardless of where the
pointing device is on the touch screen because some
voltage is lost across the internal switches. This situa-
tion can be remedied if use differential reference mode
GND
Y+
X+
Y-
+Vcc
VREF
+IN
-IN
Converter
+REF
-REF
Y Switch ON
GND
FIGURE 3.Single-Ended Reference Mode
(SER/
High, A2=Low,A1=Low,A0=High)
As shown in Figure 4,by setting the SER/
bit
LOW, the +REF and -REF inputs are connected di-
rectly to Y+ and Y-. This makes the analog-to- digital
conversion ratiometric.
The result of the conversion is always a percentage
of the external resistance, reardless of how it changes
in relation to the on-resistance of the internal switches.
Note that there is an important consideration regard-
ing power dissipation when using the ratiometric mode
of operation,the external device should powered
throughout the acquisition and conversion periods.
Differential reference mode
Figure 4. Differential Reference Mode
(SER/
LOW, A2=Low,A1=Low,A0=High)
Data is written to,and read from , the APT7843 via
the serial port. The serial port has 4 pins - serial
clock (DCLK),chip select (
) ,data in (DIN) and
data out (DOUT). The DCLK acts on the rising edge.
The
acts as a reset for the serial port with
goes
low initating a conversion cycle. The cycle consists
of 2 parts - a write followed by a read. Figure 5
shows the typical timing of the APT7843’s serial
interface. A total of 24 clock cycles will complete
one conversion.
Also shown in Figure 5 is the placement and order of
the control bits within the control byte. Tables III and
IV give detailed information about these bits.
The first bit, the
′S′ bit, must always be HIGH and
indicates the start of the control byte. The APT7843
will ignore inputs on the DIN pin until the start bit S
detected.
The next three bits (A2 - A0) select the active input
channel or channels of the input multiplexer (see Tables
I and II and Figure 2).
The MODE bit determines the number of bits for each
conversion, either 12 bits (LOW) or 8 bits (HIGH).
The SER/
bit controls the reference mode: either
single-ended (HIGH) or differential (LOW). (The dif-
ferential mode is also referred to as the ratiometric
conversion mode.)
The last two bits (PD1 - PD0) select the power- down
mode as shown in Table V. If both inputs are HIGH,
the device is always powered up. If both inputs are
LOW, the device enters a power-down mode be-
tween conversions.
Serial Interface
CS
DFR
CS
DFR
CS
DFR
GND
Y+
X+
Y-
+Vcc
Y+
+IN
-IN
Converter
+REF
-REF
Y Switch ON
Y-
DFR
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